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Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems

Janani Mukundan, Hillery Hunter, Kyu-hyoun Kim, Jeffrey Stuecheli, José F. Martínez
2013 SIGARCH Computer Architecture News  
When looking at the refresh problem more closely, we identify in high-density DRAM systems a phenomenon that we call command queue seizure, whereby the memory controller's command queue seizes up temporarily  ...  In this paper, we first conduct an analysis of DDR4 DRAM's FGR feature, and show that there is no one-size-fits-all option across a variety of applications.  ...  This work was supported in part by NSF Award CNS-0720773.  ... 
doi:10.1145/2508148.2485927 fatcat:bzxl4bpcija3noa67x37pphfx4

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems

Janani Mukundan, Hillery Hunter, Kyu-hyoun Kim, Jeffrey Stuecheli, José F. Martínez
2013 Proceedings of the 40th Annual International Symposium on Computer Architecture - ISCA '13  
When looking at the refresh problem more closely, we identify in high-density DRAM systems a phenomenon that we call command queue seizure, whereby the memory controller's command queue seizes up temporarily  ...  In this paper, we first conduct an analysis of DDR4 DRAM's FGR feature, and show that there is no one-size-fits-all option across a variety of applications.  ...  This work was supported in part by NSF Award CNS-0720773.  ... 
doi:10.1145/2485922.2485927 dblp:conf/isca/MukundanHKSM13 fatcat:ftskmc5c4jadde7meb2qkhxm2a

Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques [article]

Jeremie S. Kim and Minesh Patel and A. Giray Yaglikci and Hasan Hassan and Roknoddin Azizi and Lois Orosa and Onur Mutlu
2020 arXiv   pre-print
In order to shed more light on how RowHammer affects modern and future devices at the circuit-level, we first present an experimental characterization of RowHammer on 1580 DRAM chips (408x DDR3, 652x DDR4  ...  , and 520x LPDDR4) from 300 DRAM modules (60x DDR3, 110x DDR4, and 130x LPDDR4) with RowHammer protection mechanisms disabled, spanning multiple different technology nodes from across each of the three  ...  Acknowledgments We thank the anonymous reviewers of ISCA 2020 for feedback and the SAFARI group members for feedback and the stimulating intellectual environment they provide.  ... 
arXiv:2005.13121v2 fatcat:ucz46snqqnbt3br3kdazlfhzl4

Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins [article]

Jeremie S. Kim
2021 arXiv   pre-print
Overall, our studies build a new understanding of modern DRAM devices to improve computing system performance, reliability and security all at the same time.  ...  We demonstrate with our characterization of real chips, that existing RowHammer mitigation mechanisms either are not scalable or suffer from prohibitively large performance overheads in projected future  ...  node size scales and existing RowHammer mitigation mechanisms either do not scale or have prohibitively high overheads to mitigate RowHammer bit flips in future DRAM chips.  ... 
arXiv:2109.14520v1 fatcat:7hhrlz3tfjgx5fekdblfawxf3a

Mitigating the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration [article]

Chao-Hsuan Huang, Ishan G Thakkar
2020 arXiv   pre-print
In this paper, we show that reorganizing DRAM cell-arrays using the emerging monolithic 3D (M3D) integration technology can mitigate these fundamental latency-area tradeoffs.  ...  product (EDP), with up to 14% less DRAM die area, com-pared to the conventional 2D DDR4 DRAM.  ...  These results corroborate the excellent capabilities of the M3D technology in mitigating the fundamental latency-area tradeoffs for DRAMs, to achieve simultaneous benefits in DRAM access latency and per-die  ... 
arXiv:2008.11367v1 fatcat:ivyn3eiikbhwdj7vw3npm2sg7q

ZEM: Zero-cycle Bit-masking Module for Deep Learning Refresh-less DRAM

Duy-Thanh Nguyen, Nhut-Minh Ho, Minh-Son Le, Weng-Fai Wong, Ik-Joon Chang
2021 IEEE Access  
ACKNOWLEDGMENT This research was supported by National R&D Program through the National Research Foundation of Korea(NRF) funded by Ministry of Science and ICT (2020M3F3A2A01085755).  ...  CONCLUSION In this paper, we have presented the encoding scheme that enables refresh-less DRAM for high-performance and energyefficient deep learning system called ZEM.  ...  DRAM Type Density Timing model Energy Model ECC overhead (ns) LPDDR3 -32bit DDR4 -64bit HBM -128bit (Legacy) 16Gb 16Gb 16Gb JESD209-3C [42] JESD79-4B [43] JESD235C [36] GEM5 GEM5 Borrowed  ... 
doi:10.1109/access.2021.3088893 fatcat:goa2xnsgnfa6bai5x2bujilnxa

CAM-based retention-aware DRAM (CRA-DRAM) for refresh power reduction

Yong Ye, Yuan Du, Weiliang Jing, Xiaoyun Li, Zhitang Song, Bomy Chen
2017 IEICE Electronics Express  
As the size and speed of DRAM devices continue to increase, the overhead of refresh has caused a great power and performance dissipation.  ...  In this paper, we proposed a CAM (content-addressable memory)-based Retention-Aware DRAM (CRA-DRAM) system, a hardware implementation that uses CAM and RAM to locate and replace the leaky cells at the  ...  .: "Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems," ISCA (2013) 48 (DOI: 10.1145/2485922.2485927).  ... 
doi:10.1587/elex.14.20170053 fatcat:2v4pwkznrvglrlris5gjtqj6kq

Reducing DRAM Refresh Overheads with Refresh-Access Parallelism [article]

K. K. Chang, D. Lee, Z. Chishti, A. R. Alameldeen, C. Wilkerson, Y. Kim, O. Mutlu
2018 arXiv   pre-print
their performance bene ts increase as DRAM density increases.  ...  To mitigate the negative performance impact of DRAM refresh, our HPCA 2014 paper proposes two complementary mechanisms, DARP (Dynamic Access Refresh Parallelization) and SARP (Subarray Access Refresh Parallelization  ...  This research was supported in part by the Intel Science and Technology Center on Cloud Computing, the Semiconductor Research Corporation, and an NSF CAREER Award (grant 0953246).  ... 
arXiv:1805.01289v1 fatcat:fwwi4pdh3fhdhf2j4og44itmp4

CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture

Tao Zhang, Matt Poremba, Cong Xu, Guangyu Sun, Yuan Xie
2014 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)  
To mitigate the refresh penalty, a Concurrent-REfresh-Aware Memory system (CREAM) is proposed in this work so that memory access and refresh can be served in parallel.  ...  As DRAM density keeps increasing, more rows need to be protected in a single refresh with the constant refresh number.  ...  Consequently, the DRAM system should be carefully designed to mitigate the refresh penalty.  ... 
doi:10.1109/hpca.2014.6835947 dblp:conf/hpca/ZhangPXSX14 fatcat:lpwxedokhne7pa6bhvxfocuyqu

Refresh pausing in DRAM memory systems

Prashant J. Nair, Chia-Chen Chou, Moinuddin K. Qureshi
2014 ACM Transactions on Architecture and Code Optimization (TACO)  
It provides an average performance improvement of 5.1% for 8Gb devices and becomes even more effective for future high-density technologies.  ...  It exploits the property that each refresh operation in a typical DRAM device internally refreshes multiple DRAM rows in JEDEC-based distributed refresh mode.  ...  combination of the following reasons: (1) High Density: As the number of rows in the DRAM array increases, so does the number of rows in a refresh bundle.  ... 
doi:10.1145/2579669 fatcat:nctztd5bsrenzbaf6wy3a4jrtq

CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off [article]

Haocong Luo, Taha Shahroodi, Hasan Hassan, Minesh Patel, Abdullah Giray Yaglikci, Lois Orosa, Jisung Park, Onur Mutlu
2020 arXiv   pre-print
density as a density-optimized commodity DRAM chip and 2) high-performance mode, where two adjacent DRAM cells in a DRAM row and their sense amplifiers are coupled to operate as a single low-latency logical  ...  Our evaluations show that CLR-DRAM can improve system performance and DRAM energy consumption by 18.6% and 29.7% on average with four-core multiprogrammed workloads.  ...  We acknowledge the generous gifts provided by our industrial partners: Alibaba, Facebook, Google, Huawei, Intel, Microsoft, and VMware.  ... 
arXiv:2005.12775v1 fatcat:lj4fyi4ssjgldovtt3jebnd2fm

Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices [article]

A. Giray Yağlıkçı, Haocong Luo, Geraldo F. de Oliviera, Ataberk Olgun, Minesh Patel, Jisung Park, Hasan Hassan, Jeremie S. Kim, Lois Orosa, Onur Mutlu
2022 arXiv   pre-print
RowHammer is a circuit-level DRAM vulnerability, where repeatedly activating and precharging a DRAM row, and thus alternating the voltage of a row's wordline between low and high voltage levels, can cause  ...  Our work closes this gap in understanding. This is the first work to experimentally demonstrate on 272 real DRAM chips that lowering VPP reduces a DRAM chip's RowHammer vulnerability.  ...  We acknowledge the generous gifts provided by our industrial partners, including Google, Huawei, Intel, Microsoft, and VMware, and support from the Microsoft Swiss Joint Research Center.  ... 
arXiv:2206.09999v1 fatcat:pjz3zul2prg5bdzgfdmbh5hjta

A Case for Transparent Reliability in DRAM Systems [article]

Minesh Patel, Taha Shahroodi, Aditya Manglik, A. Giray Yaglikci, Ataberk Olgun, Haocong Luo, Onur Mutlu
2022 arXiv   pre-print
To support our argument, we study four ways that system designers can adapt commodity DRAM chips to system-specific design goals: (1) improving DRAM reliability; (2) reducing DRAM refresh overheads; (3  ...  ) reducing DRAM access latency; and (4) mitigating RowHammer attacks.  ...  Kim, Hasan Hassan, Joel Lindegger, and Meryem Banu Cavlak for the feedback they provided on earlier versions of this paper.  ... 
arXiv:2204.10378v1 fatcat:h4i54ktlybfrvd63bgpwpdcllu

A case for Refresh Pausing in DRAM memory systems

P. Nair, Chia-Chen Chou, M. K. Qureshi
2013 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)  
It provides an average performance improvement of 5.1% for 8Gb devices, and becomes even more effective for future high-density technologies.  ...  It exploits the property that each refresh operation in a typical DRAM device internally refreshes multiple DRAM rows in JEDEC-based distributed refresh mode.  ...  Acknowledgments Thanks to Jeff Stuecheli and Rajeev Balasubramonian for discussions and feedback. Moinuddin Qureshi is supported by NetApp Faculty Fellowship and Intel Early Career Award.  ... 
doi:10.1109/hpca.2013.6522355 dblp:conf/hpca/NairCQ13 fatcat:mdxxxpqkh5cktbhgkzlfsl2m2y

Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications [article]

Hasan Hassan, Yahya Can Tugrul, Jeremie S. Kim, Victor van der Veen, Kaveh Razavi, Onur Mutlu
2021 arXiv   pre-print
The RowHammer vulnerability in DRAM is a critical threat to system security.  ...  At a high level, TRR detects and refreshes potential RowHammer-victim rows, but its exact implementations are not openly disclosed.  ...  At a high level, TRR detects and refreshes cost of DRAM [81].  ... 
arXiv:2110.10603v1 fatcat:ab7zgdwb3vaqtbszjmyxuvngny
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