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UltraSPARC-I

James Gateley, Dale Greenley, Miriam Blatt, Dennis Chen, Scott Cooke, Piyush Desai, Manjunath Doreswamy, Mark Elgood, Gary Feierbach, Tim Goldsbury
1995 Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95  
The next generation UltraSPARC-I CPU represents a significant step forward in processor performance at the cost of increased design complexity.  ...  Discussed are the goals, methods and results of the UltraSPARC-I emulation. 32nd ACM/IEEE Design Automation Conference ®  ...  The UltraSPARC-I CPU from SPARC Technology, a division of Sun Microsystems, Inc., is a high-performance 64-bit V9 SPARC implementation 100% compatible with existing binaries [1] [2] [3] [4] [5] [6  ... 
doi:10.1145/217474.217483 dblp:conf/dac/GateleyBCCDDEFGGJKKMNNOPSSWW95 fatcat:zgrrbfbvpvhf7hq2huqhwi7njy

UltraSparc I: a four-issue processor supporting multimedia

M. Tremblay, J.M. O'Connor
1996 IEEE Micro  
Acknowledgments We acknowledge the work of other members of the architecmre team, specifically L. Kohn  ...  Itrasparc I is a second-generation superscalar processor. It is a highperformance, highly integrated, fourissue superscalar processor based on the Sparc Version 9 64-bit RISC architecture.  ...  UltraSparc's design implements multilevel trap registers as specified by the 64-bit Sparc Version 9 instruction set architecture The five trap levels that the architecture supports reduce system overhead  ... 
doi:10.1109/40.491461 fatcat:njvvxxikobak5moljqyvxhwwv4

The design of the microarchitecture of UltraSPARC-I

M. Tremblay, D. Greenley, K. Normoyle
1995 Proceedings of the IEEE  
This paper describes not only the microarchitecture of UltraSPARC-I, a 167 MHz 64-b fourway superscalar processor, but more importantly it presents the analysis and tradeoffs that were made "en route"  ...  to the$nal chip.  ...  ACKNOWLEDGMENT The authors would like to acknowledge Les Kohn and Bill Joy for their contribution to the microarchitecture, and the whole UltraSPARC team for actually delivering the chip!  ... 
doi:10.1109/5.476081 fatcat:6xnbppognzftfihb5m622jpgye

A dual-core 64b ultraSPARC microprocessor for dense server applications

Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Su, Ana Sonia Leon
2004 Proceedings of the 41st annual conference on Design automation - DAC '04  
ACKNOWLEDGMENTS The authors acknowledge contributions from the entire Gemini development team and all those who supported the project both at Sun Microsystems and Texas Instruments.  ...  DeSantis for supporting the project.  ...  The data array has 8 ECC bits for 64b data with SEC/DED (single bit error correction/double bit error detection). The tag array is protected by parity bits.  ... 
doi:10.1145/996566.996750 dblp:conf/dac/TakayanagiSPSL04 fatcat:hhg5biswyzbi7j2hcpntduduii

A dual-core 64-bit ultraSPARC microprocessor for dense server applications

T. Takayanagi, J.L. Shin, B. Petrick, J.Y. Su, H. Levy, Ha Pham, J. Son, N. Moon, D. Bistry, U. Nair, M. Singh, V. Mathur (+1 others)
2005 IEEE Journal of Solid-State Circuits  
A dual-core 64-bit microprocessor optimized for compute-dense systems such as rack-mount and blade servers for network computing was developed.  ...  The chip consists of two Ultra-SPARC II cores, each with its own 512 kB L2 cache, a DDR-1 memory controller, and symmetric multiprocessor bus (JBus) controllers.  ...  Currently, he is the Integration Lead for the next-generation multithreading SPARC processor.  ... 
doi:10.1109/jssc.2004.838023 fatcat:pdfny6iuzzc57ic6xcq3u6dlt4

UltraSPARC-II/: expanding the boundaries of a system on a chip

K.B. Normoyle, M.A. Csoppenszky, A. Tzeng, T.P. Johnson, C.D. Furman, J. Mostoufi
1998 IEEE Micro  
T he central mission of the UltraSPARC-IIi is optimized price/performance and ease of use for the system designer.  ...  The net result of a system containing an UltraSPARC-IIi will realize a substantial cost savings.  ...  Acknowledgments Tremendous thanks and appreciation go to the entire UltraSPARC-IIi project team. Without the hard work of many people, UltraSPARC-IIi would not exist today.  ... 
doi:10.1109/40.671399 fatcat:sc3kknyvbfgmlk5rpda55k4bji

UltraSPARC-II: the advancement of ultracomputing

G. Goldman, P. Tirumalai
COMPCON '96. Technologies for the Information Superhighway Digest of Papers  
UltraSPARC-II extends the family of Sun's 64-bit SPARC V9 microprocessors, building on the UltraSPARC-I pipeline and adding critical enhancements to boost data bandwidth, hide memory latency, and improve  ...  This paper describes the motivation and implementation of UltraSPARC-II's enhancements.  ...  Acknowledgments The design and implementation of UltraSPARC-II relied on the efforts of many individuals in logic design, circuit design, CAD, verification, emulation, and system and product engineering  ... 
doi:10.1109/cmpcon.1996.501804 dblp:conf/compcon/GoldmanT96 fatcat:o3ymbrgolbauxagv5kbhoubjym

64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency

R. Heald, K. Shin, V. Reddy, I-Feng Kao, M. Khan, W.L. Lynch, G. Lauterbach, J. Petolino
1998 IEEE Journal of Solid-State Circuits  
Address base-plus-offset summing is merged into the decode structure of this 64-KByte (512-Kbit), four-way setassociative cache.  ...  On UltraSPARC III, he contributed to the design of the SAM Data Cache and physical TAG arrays.  ...  ACKNOWLEDGMENT The authors gratefully acknowledge the support of their colleagues in the Sun Microsystems, Microelectronics Division, SRAM group.  ... 
doi:10.1109/4.726558 fatcat:t4qy3xx3kza2blutfzpzd44xc4

Computer arithmetic and hardware: "off the shelf" microprocessors versus "custom hardware"

Daniel Etiemble
2002 Theoretical Computer Science  
By comparing their evolution over the last 10 years, we show that the performance of arithmetic operators is far less critical than the performance of the memory hierarchy or the branch predictors.  ...  First, we examine the impact of computer arithmetic on the overall performance of today's microprocessors.  ...  Acknowledgements I would like to thank Professor Zvonko Vranesic of the University of Toronto in Ontario, Canada for his help in correcting and polishing English in this article.  ... 
doi:10.1016/s0304-3975(00)00424-2 fatcat:trzfntxn55avhctr665zflyccq

A chip multithreaded processor for network-facing workloads

S. Kapil, H. McGhan, J. Lawrendra
2004 IEEE Micro  
The processor described in this article is a member of Sun's first generation of CMT processors designed to efficiently execute network-facing workloads.  ...  Similarly, a CMT processor might seek to use power more efficiently by clocking at a lower frequency-if this tradeoff lets it generate more work per watt of expended power.  ...  Acknowledgments This article, like the project it describes, was a collaborative effort.  ... 
doi:10.1109/mm.2004.1289288 fatcat:6qryksp4nbd4fdk7ermbtdaumy

A dual-core 64 b UltraSPARC microprocessor for dense server applications

T. Takayanagi, J.L. Shin, B. Petrick, J. Su, H. Levy, H. Pham, J. Son, N. Moon, D. Bistry, M. Singh, V. Mathur, A.S. Leon
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)  
ACKNOWLEDGMENTS The authors acknowledge contributions from the entire Gemini development team and all those who supported the project both at Sun Microsystems and Texas Instruments.  ...  DeSantis for supporting the project.  ...  The data array has 8 ECC bits for 64b data with SEC/DED (single bit error correction/double bit error detection). The tag array is protected by parity bits.  ... 
doi:10.1109/isscc.2004.1332592 fatcat:mcyqnttutrdjpijkgrbsxjpu4y

The Comparisons of OpenCL and OpenMP Computing Paradigm

Slo-Li Chu, Chih-Chieh Hsiao
2014 Applied Mathematics & Information Sciences  
This work demonstrates the capabilities of OpenCL with several platforms, based on a preliminary example.  ...  The proposed benchmarks with different attributes are implemented by OpenMP and OpenCL sequentially to compare their differences.  ...  Acknowledgement This work is supported in part by the National Science Council of Republic of China, Taiwan under Grant NSC 100-2221-E-033-043.  ... 
doi:10.12785/amis/081l42 fatcat:r2clxenj6nhbjkoi3iqnnfk2k4

Decisive Aspects in the Evolution of Microprocessors

H. Falk
2004 Proceedings of the IEEE  
We show that designers increased the throughput of the microarchitecture at the instruction level basically by the subsequent introduction of temporal, issue and intra-instruction parallelism in such a  ...  =6 6,0$ 0(0%(5 ,((( The incessant demand for higher performance has provoked a dramatic evolution of the microarchitecture of high performance microprocessors.  ...  E.g. in Intel's MMX multimedia extension [82] , the PADDW MM1, MM2 SIMD instruction carries out four fixed point additions on the four 16-bit operand pairs held in the 64-bit registers MM1 and MM2.  ... 
doi:10.1109/jproc.2004.837615 fatcat:3liaxjrdcje3rddzxtm52kagtu

Parallelism via Multithreaded and Multicore CPUs

A.C. Sodan, J. Machina, A. Deshmeh, K. Macnaughton, B. Esbaugh
2010 Computer  
The additional capacity was used in the past for development of superscalar CPUs with replicated execution units and deep pipelines to exploit instruction-level parallelism.  ...  the gains possible from further raising processor frequency.  ...  Integrating a GPU core on chip is another possibility which is currently planned by several vendors for next-generation CPUs.  ... 
doi:10.1109/mc.2010.75 fatcat:z34ptnd3rbgdvf7md5dmmqinfm

A survey of processors with explicit multithreading

Theo Ungerer, Borut Robič, Jurij Šilc
2003 ACM Computing Surveys  
Hardware multithreading is becoming a generally applied technique in the next generation of microprocessors.  ...  Simultaneous multithreaded processors combine the multithreading technique with a wide-issue superscalar processor to utilize a larger part of the issue bandwidth by issuing instructions from different  ...  ACKNOWLEDGMENTS The authors would like to thank anonymous reviewers for many valuable comments.  ... 
doi:10.1145/641865.641867 fatcat:u6x7jdmkfvexnm3culskjsoxwi
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