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CMOS Low-Dropout Voltage Regulator Design Trends: An Overview
2022
Electronics
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Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. ...
Systems-on-Chip's (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today's devices. ...
Thus, to simulate the developed LDO under these dynamic conditions, the clock frequency is initially fck = 250 kHz (typical of a low-power mode operation). ...
doi:10.3390/electronics11020193
fatcat:d6c3zifp3vexzjixalmupuqgfy
2020 Index IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 67
2020
IEEE Transactions on Circuits and Systems - II - Express Briefs
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., A Novel Dynamic Detection for Flash Memory; 600-604 Issakov, V., see Aguilar, E., TCSII May 2020 906-910 Iu, H.H., see Lai, Q., 1129-1133 Iu, H.H., see Xu, G., TCSII Dec. 2020 3452-3456 Iu, H.H.C ...
1074-1078 Iu, H.H.C., see Eshraghian, J.K., TCSII May 2020 956-960 Iu, H.H.C., see Yu, D., 1334-1338 Iu, H.H.C., see Wang, L., TCSII Oct. 2020 2084-2088 J Jabavathi, J.D., and Sait, H., Design of ...
., +, TCSII June 2020 1069-1073 Robust Design Strategy of Quantized Feedback Control. Chang, X., +, TCSII Capless LDO With 30-dB PSRR at 10-kHz Using a Lightweight Local Generated Supply. ...
doi:10.1109/tcsii.2020.3047305
fatcat:ifjzekeyczfrbp5b7wrzandm7e
Σταθεροποιητής τάσης πολύ χαμηλής ενεργειακής κατανάλωσης για εφαρμογές ασύρματων δικτύων αισθητήρων:
2014
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Also when no load is connected to the regulator, the quiescent current of LDO does not exceed 500nA so the maximum power efficiency is close to 94.1%. ...
In this work is presented a low quiescent current Low Dropout voltage regulator with two type of compensation. For external compensation is used a 4.7uF capacitor and for internal a 20pF capacitor. ...
, και Marcelino Santos,
ScienceDirect.com - Microelectronics Journal – ‘Ultra low power capless LDO
with dynamic biasing of derivative feedback’.
[15] S. ...
doi:10.26262/heal.auth.ir.135972
fatcat:q27mkbcsu5gftl4l3rhebtlxrm
Power Management Circuits for Front-End ASICs Employed in High Energy Physics Applications
[article]
2018
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, with a particular focus on the minimisation of interference noise from power management circuitry. ...
A prototype test chip with power management IP blocks was fabricated, using a TSMC 65 nm CMOS technology. ...
for power and biasing of front-end electronics modules using a power supply in the order of 1.0 V -1.2 V . ...
doi:10.6092/polito/porto/2713038
fatcat:qal3rauwqzgmbdby3j3o3sxqky