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A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC Architectures

H. Chtioui, S. Niar Lamih, R. B. Atitallah, M. Zahren, JL. Dekeyser, M. Abid
2012 International Journal of Computer Applications  
Moreover, one of the main factors affecting the performance of such systems is the management of cache coherency problem. In this context, we propose a new cache-coherency protocol.  ...  The proposed protocol is able to dynamically adapt its functioning mode according to variations in application memory access patterns.  ...  BACKGROUND AND PREVIOUS WORK Existing hybrid protocols for coherency management in multiprocessor architectures [1] [2], can be classified into two families: On-line hybrid protocol In on-line hybrid  ... 
doi:10.5120/7172-9801 fatcat:uy52gzhryfbercxl6rczif5kba

Coherence Protocols for Bus-Based and Scalable Multiprocessors, Internet, and Wireless Distributed Computing Environments: A Survey [chapter]

John Sustersic, Ali Hurson
2003 Advances in Computers  
Second, hybrid and adaptive coherence organizations have proven effective in improving coherence protocol performance in bus-based multiprocessors.  ...  The hybrid Update-Once protocol and the adaptive AHDMS protocol require three bits per block for this purpose.  ... 
doi:10.1016/s0065-2458(03)59005-2 fatcat:hrflfqanffa7bo4dmj2l32pzba

1-to-Many and many-to-1 communication in hybrid wireless network-on-chip

Tao Jin, Shuai Wang
2013 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)  
Since 1-to-many and many-to-1 communications caused by the cache coherence protocol in the multiprocessor system have high demands on the network, we propose several optimization schemes to improve both  ...  1-to-many and many-to-1 communications in the hybrid WiNoC.  ...  Two different cache coherence protocols, HyperTransport (HT) [18] and Token Coherence (TC) [19] , are evaluated. B.  ... 
doi:10.1109/icecs.2013.6815462 dblp:conf/icecsys/JinW13 fatcat:h3ihafzp6fcajdeptos73suxqy

Hybrid Update/Invalidate Schemes for Cache Coherence Protocols [article]

Roman Dovgopol, Matthew Rosonke
2015 arXiv   pre-print
In general when considering cache coherence, write back schemes are the default. These schemes invalidate all other copies of a data block during a write.  ...  In this paper we propose several hybrid schemes that will switch between updating and invalidating on processor writes at runtime, depending on program conditions.  ...  This can be easily accomplished by the directory in any cache coherence protocol that uses one.  ... 
arXiv:1502.00101v1 fatcat:hja63wemd5hdxgb6lagjthgivq

Enhancing Cache Coherent Architectures with access patterns for embedded manycore systems

Jussara Marandola, Stephane Louise, Loic Cudennec, Jean-Thomas Acquaviva, David A. Bader
2012 2012 International Symposium on System on Chip (SoC)  
In this paper, we propose to analyze this component and its associated protocol that enhance a cache coherent system to perform speculative requests when access patterns are detected.  ...  In this paper, we present a Cache Coherent Architecture that optimizes memory accesses to patterns using both a hardware component and specialized instructions.  ...  In figure 5 , we compared two approaches of cache coherency protocols for a cache miss case.  ... 
doi:10.1109/issoc.2012.6376369 dblp:conf/issoc/MarandolaLCAB12 fatcat:3ovjidxtgfendpydlbes4uzqgu

Hybrid Shared-aware Cache Coherence Transition Strategy

Sun Sun, Hong An, Junshi Junshi Chen
2015 International Journal of Hybrid Information Technology  
shared-aware cache coherence transition strategy which collaborate with directory-based MESI cache coherence protocol.  ...  Results show the whole performance gains of up to 21% opposed to the traditional write-invalidate cache coherence transition strategy.  ...  Kurian [14] propose a locality-aware adaptive coherence protocol to manage the distributed private caches in CMPs.  ... 
doi:10.14257/ijhit.2015.8.2.34 fatcat:toxoolstwrb73mqccwnlexfyyi

PSCR: a coherence protocol for eliminating passive sharing in shared-bus shared-memory multiprocessors

R. Giorgi, C.A. Prete
1999 IEEE Transactions on Parallel and Distributed Systems  
Many protocols use smart solutions to limit the overhead to maintain coherence among shared copies.  ...  Our protocol further limits the coherence-maintaining overhead by using information about access patterns to shared data exhibited in parallel applications.  ...  Adaptive Hybrid Protocols Adaptive Hybrid (AH) protocols dynamically switch between WU and WI policies or are pattern-sensitive, modifying the basic protocol behavior to manage the necessary coherence  ... 
doi:10.1109/71.780868 fatcat:c44pju2v5fgm3ozmltso7pz2nu

Evaluation of a Competitive-Update Cache Coherence Protocol with Migratory Data Detection

Håkan Grahn, Per Stenström
1996 Journal of Parallel and Distributed Computing  
Although directory-based write-invalidate cache coherence protocols have a potential to improve the performance of large-scale multiprocessors, coherence misses limit the processor utilization.  ...  We propose in this study to extend a competitive-update protocol with a previously published adaptive mechanism that can dynamically detect migratory objects and reduce the coherence traffic they cause  ...  Acknowledgments We would like to thank Lars Jönsson for implementing the basic adaptive protocol in our simulator as a part of his Master's thesis.  ... 
doi:10.1006/jpdc.1996.0164 fatcat:a6a6nrmkrfcmbjvyz7jwxgjniq

Boosting the performance of shared memory multiprocessors

P. Stenstrom, M. Brorsson, F. Dahlgren, H. Grahn, M. Dubois
1997 Computer  
Most such machines incorporate caches in each node, to allow data replication, and use a cache coherence protocol to ensure that a processor accesses the latest copy of the replicated data.  ...  An emerging class of shared memory multiprocessors-nonuniform memory access machines with private caches and a cache coherence (CC) protocol-use a directory-based write-invalidate scheme.  ...  This can cut down the traffic caused by updates even more than protocols like the hybrid update/invalidate protocol just described.  ... 
doi:10.1109/2.596630 fatcat:igee7gkc2vhk7oyrjstlwzvz3q

A General Adaptive Cache Coherency-Replacement Scheme for Distributed Systems [chapter]

Jose Aguilar, Ernst Leiss
2001 Lecture Notes in Computer Science  
We propose an adaptive cache coherence-replacement scheme for distributed systems that is based on several criteria about the system and applications, with the objective of optimizing the distributed cache  ...  We examine different distributed platforms (shared memory systems, distributed memory systems, and web proxy cache systems) and the potential of incorporating coherency-replacement issues in the cache  ...  There are two classes of cache coherence protocols [12] : write-invalidate and writeupdate.  ... 
doi:10.1007/3-540-48206-7_10 fatcat:2sgdt4prqnehjk3jyjfjxhjoou

A Web Proxy Cache Coherency and Replacement Approach [chapter]

Jose Aguilar, Ernst Leiss
2001 Lecture Notes in Computer Science  
We propose an adaptive cache coherence-replacement scheme for web proxy cache systems that is based on several criteria about the system and applications, with the objective of optimizing the distributed  ...  Our coherence-replacement scheme assigns a replacement priority value to each cache block according to a set of criteria to decide which block to remove.  ...  There are two classes of cache coherence protocols [14] : write-invalidate and write-update.  ... 
doi:10.1007/3-540-45490-x_8 fatcat:4vs4tqx3zjdnloqyf7x4otzhvq

Exploiting multicast messages in cache-coherence protocols for NoC-based MPSoCs

Tales M. Chaves, Everton A. Carara, Fernando G. Moraes
2011 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)  
Differently from previous works, we investigate the benefits NoCs can bring to directory-based cache coherence protocols using RTL modeling.  ...  Such method is not suitable for cache coherence protocols, because transactions as block invalidate and block update are naturally multicast.  ...  Cache coherence between shared memory and caches is ensured by a hybrid implementation of a MSI protocol.  ... 
doi:10.1109/recosoc.2011.5981492 dblp:conf/recosoc/ChavesCM11 fatcat:zrxbt3upi5djri3apzas5p4m2y

A Hybrid Shared Memory/Message Passing Parallel Machine

Matthew I. Frank, Mary K. Vernon
1993 1993 International Conference on Parallel Processing - ICPP'93 Vol1  
The SM/MP architecture contains both a high-performance coherence protocol for shared memory, and message-passing primitives that coexist with the coherence protocol but have no coherence overhead.  ...  In this paper we propose a hybrid SM/MP architecture together with a hybrid SM/MP programming model, that we believe effectively combines the advantages of each system.  ...  Below we illustrate this for a generic directory-based cache coherence protocol with cache block states exclusive, shared, and invalid.  ... 
doi:10.1109/icpp.1993.25 dblp:conf/icpp/FrankV93 fatcat:wzdwquinpzejlgktooiowwdjum

Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessors

Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, David A. Wood
2003 SIGARCH Computer Architecture News  
Recently proposed hybrid protocols trade-off latency and bandwidth by directly sending requests to a predicted destination set.  ...  Snooping protocols send requests to the maximal destination set (i.e., all processors), reducing latency for cache-to-cache misses at the expense of increased traffic.  ...  Other hybrid protocols adapt between writeinvalidate and write-update [4, 9, 15, 26, 31] , by migrating data near to where it is being used [10, 14, 35] or by adapting to available bandwidth [24] .  ... 
doi:10.1145/871656.859642 fatcat:ps4egvgxh5ca5abiwfuodklgxe

Implementation and evaluation of update-based cache protocols under relaxed memory consistency models

Håkan Grahn, Per Stenström, Michel Dubois
1995 Future generations computer systems  
Invalidation-based cache coherence protocols have been extensively studied in the context of large-scale shared-memory multiprocessors.  ...  By contrast, update-based protocols have a potential to reduce both write and read penalties under relaxed memory consistency models because coherence misses can be completely eliminated.  ...  the cache coherence protocols.  ... 
doi:10.1016/0167-739x(94)00067-o fatcat:w4hucg77hzhgrfson4sjih2rme
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