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IBM POWER7 multicore server processor

B. Sinharoy, R. Kalla, W. J. Starke, H. Q. Le, R. Cargnoni, J. A. Van Norstrand, B. J. Ronchetti, J. Stuecheli, J. Leenstra, G. L. Guthrie, D. Q. Nguyen, B. Blaner (+3 others)
2011 IBM Journal of Research and Development  
Fabricated in IBM's 45-nm silicon-on-insulator (SOI) technology with 11 levels of metal, the chip contains more than one billion transistors.  ...  In this paper, we describe the key features of the POWER7 A processor chip. On the chip is an eight-core processor, with each core capable of four-way simultaneous multithreaded operation.  ...  Acknowledgments This paper is based upon work supported by the Defense Advanced Research Projects Agency under its Agreement No. HR0011-07-9-0002.  ... 
doi:10.1147/jrd.2011.2127330 fatcat:kztcasllyvgs5cuvzyf54myeyy

IBM POWER8 processor core microarchitecture

B. Sinharoy, J. A. Van Norstrand, R. J. Eickemeyer, H. Q. Le, J. Leenstra, D. Q. Nguyen, B. Konigsburg, K. Ward, M. D. Brown, J. E. Moreira, D. Levitan, S. Tung (+8 others)
2015 IBM Journal of Research and Development  
Combined with a 50% increase in the number of cores (from 8 in the POWER7 processor to 12 in the POWER8 processor), the result is a processor that leads the industry in performance for enterprise workloads  ...  single-core throughput of the POWER7 processor in several commercial applications.  ...  Acknowledgments A large number of people worked on the POWER8 processor core microarchitecture described in this paper.  ... 
doi:10.1147/jrd.2014.2376112 fatcat:oylmygytvbej3cm3m54uv66fhy

Characterizing the energy consumption of data transfers and arithmetic operations on x86−64 processors

Daniel Molka, Daniel Hackenberg, Robert Schone, Matthias S. Muller
2010 International Conference on Green Computing  
For example, in case of the SPECPower benchmark the workload is a typical web server specific Java application.  ...  The contribution of individual components is usually not considered in this class of benchmarks.  ...  ACKNOWLEDGMENT The authors would like to thank Intel Germany for providing us with the Westemere-EP test system.  ... 
doi:10.1109/greencomp.2010.5598316 dblp:conf/green/MolkaHSM10 fatcat:hgym2j4vyva2dntb3dq4ocrrcm

D5.2: Best Practices for HPC Procurement and Infrastructure

Norbert Meyer, Marcin Lawenda
2013 Zenodo  
As well as the general market analysis, this task also describes the link between hardware and software (in collaboration with software-specific work packages WP11 and WP12), providing information on the  ...  Specific areas of interest are analysed in depth in terms of the market they belong to and the general HPC landscape, with a particular emphasis on the European point of view.  ...  Coming from 32 nm (2009) via 22 nm to 14 nm (2013) Intel expects to move to 10 nm (2015+), 7 nm, and 5 nm. Going forward with scaling, new materials and device structures are needed.  ... 
doi:10.5281/zenodo.6572412 fatcat:2bqftmr5zzb7na6pnlrlxxuqnu

Active timing margin management to improve microprocessor power efficiency [article]

Yazhou Zu, 0000-0003-0047-6976, Austin, The University Of Texas At, Austin, The University Of Texas At, Vijay Janapa Reddi
2019
The author believes the optimization presented in this thesis can potentially benefit a variety of processor architectures as the conclusions are based on the solid measurement on state-of-the-art processors  ...  The key insight of this thesis is that in order to maximize active timing margin's efficiency enhancement benefits, synergistic management from processor architecture design and system software scheduling  ...  Thus, given the workload sensitiv- Active Timing Margin in the POWER7+ Multicore Processor The POWER7+ is an eight-core out-of-order processor manufactured on a 32-nm process.  ... 
doi:10.26153/tsw/1383 fatcat:putzrllx7ng3bkctqroevwdo44

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

Jeremy Hugues-Felix Constantin
2016
, dedicated to the task of random number generation alone.  ...  Pseudorandom Number Generation A pseudorandom number generator (PRNG) can be employed for the generation of the random indices.  ... 
doi:10.5075/epfl-thesis-7168 fatcat:qqbipezpknhstkk3o2t5mwjvbi

Brunina_columbia_0054D_10893.pdf [article]

2017
Processors that would otherwise be idle, being starved for data while waiting for scarce memory resources, can instead operate at high utilizations, leading to drastic improvements in the overall system  ...  By leveraging an optics-based approach, this thesis presents the design and implementation of an optically-connected memory system that exploits both the bandwidth density and distance-independent energy  ...  Each Power 775 drawer contains up to eight nodes of four POWER7 [16] processors, resulting in up to 256 POWER7 cores and 128 DIMMs (yielding 2 TB of total memory capacity).  ... 
doi:10.7916/d8rn3fzg fatcat:3hc2ac45qnccpelfneipakscfa

Learning-Based Hardware Design for Data Acquisition Systems

Cosimo Aprile
2018
The chip, fabricated in 32 nm SOI CMOS, has been flip-chip mounted on an high frequency, low loss substrate, Liquid Crystal Polymer (LCP) PCB, shown in Fig. 7.8 (left) .  ...  Learning based sampling implementations In the proposed work, we implement fully digital signal processor, which implements the Learning Based CS, described in Section 3.3.  ...  single ended receiver in 32 nm SOI CMOS, where the chip-to-chip data-rate is boosted by advanced and low-power far-end crosstalk cancellation schemes.  ... 
doi:10.5075/epfl-thesis-8693 fatcat:qfr37gbzs5cg5haehs3rvotldi

Computing architectures exploiting optical interconnect and optical memory technologies

Παύλος Π. Μανιώτης
2017
Going a step further towards highlighting the benefits of the proposed optical cache memory architecture in addressing the long-lasting "Memory Wall" problem in the computing industry, this thesis demonstrates  ...  This thesis proposes new optical systems that exploit Optical Interconnect and Optical Memory Technologies and synergizes them with processors in innovative Computing Architectures for increasing bandwidth  ...  case with the Sparc T5 processor [4.12] and Chapter 4 (2) System B corresponds to a system with the 32 KB L1d per core, double of System A, as it is the case with IBM"s Power7 processor The first to note  ... 
doi:10.26262/heal.auth.ir.294832 fatcat:4sa6cy7n65gcxj63vyxpej5woy

Architectural Exploration and Design Methodologies of Photonic Interconnection Networks

Jong Wu Chan
2017
Recent progress in silicon photonics research has enabled the demonstration of all the necessary optical building blocks for creating extremely high-bandwidth density and energy-efficient links for on-  ...  The models and tools are integrated in a novel open-source design and simulation environment called PhoenixSim. Next, we leverage PhoenixSim for the study of chip-scale photonic networks.  ...  Ring filters have been fabricated and demonstrated on SOI with 3-µm radius, corresponding to an FSR of 30 nm [29] .  ... 
doi:10.7916/d8cv4qsk fatcat:gatmxgyzlfddbez5q5ayeixfna