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Transparent Acceleration of Program Execution using Reconfigurable Hardware

Nuno Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015   unpublished
This paper introduces some of the most representative approaches for binary acceleration using reconfigurable hardware, and presents our binary acceleration approach and the latest results.  ...  The acceleration of applications, running on a general purpose processor (GPP), by mapping parts of their execution to reconfigurable hardware is an approach which does not involve program's source code  ...  RELATED WORK The acceleration of critical program sections (hot spots) by using reconfigurable hardware (RPUs) coupled to a GPP has been addressed by many research efforts.  ... 
doi:10.7873/date.2015.1122 fatcat:zvq6pepgj5ejjh5ktylp5kvcty

Seamless Hardware-Software Integration in Reconfigurable Computing Systems

M. Vuletic, L. Pozzi, P. Ienne
2005 IEEE Design & Test of Computers  
Virtualization layer for transparent programming We can achieve transparency and portability of reconfigurable applications by extending the abstraction layer-consisting of the thread library and OS support-to  ...  by using both general-purpose processors and reconfigurable hardware.  ... 
doi:10.1109/mdt.2005.44 fatcat:72taxoj22zftreulaxb6cznnuq

A Seamless Virtualization Approach for Transparent Dynamical Function Mapping Targeting Heterogeneous and Reconfigurable Systems [chapter]

Rainer Buchty, David Kramer, Fabian Nowak, Wolfgang Karl
2009 Lecture Notes in Computer Science  
We therefore present an approach targeting comfortable program development and execution, enabling full exploitation of the underlying hardware without burdening the application programmer with the details  ...  of the underlying hardware infrastructure.  ...  The concept bases on transparent and dynamic compilation and HW synthesis of Java programs to be coexecuted on general-purpose processors and reconfigurable hardware.  ... 
doi:10.1007/978-3-642-00641-8_42 fatcat:ir4xamfefze2pih3zpmjxyjqfi

Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines

Miljan VuletiĆ, Christophe Dubach, Laura Pozzi, Paolo Ienne
2005 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '05  
method by using platform-independent hardware accelerators.  ...  In contrast to the compile-once-run-anywhere concept of virtual machines, reconfigurable applications lack portability and transparent SW/HW interfacing: applicability of accelerated hardware solutions  ...  The approach improves execution times of Java programs, but it is highly dependent on the used JVM.  ... 
doi:10.1145/1084834.1084896 dblp:conf/codes/VuleticDPI05 fatcat:oul5qhgt2ve7xj435htyaosjx4

An Architecture and Programming Framework for Dynamic Reconfigurable Computing Systems

Qiang Wu, Wei Xie, Wei Wang
2006 Proceedings of the 9th Joint Conference on Information Sciences (JCIS)  
The hybrid architecture consists of microprocessors and reconfigurable hardware accelerators with corresponding control and management units.  ...  To address this issue, a framework with hybrid architecture and transparent programming model has been proposed in this paper, which allows designers develop applications independently of the underlying  ...  Acknowledgement The authors would like to thank Xilinx University Program for the kind donations of the development boards and software packages.  ... 
doi:10.2991/jcis.2006.203 dblp:conf/jcis/WuXW06 fatcat:szffmivgabahzhg4tlszjah7hi

Multithreaded virtual-memory-enabled reconfigurable hardware accelerators

Miljan Vuletic, Paolo Ienne, Christopher Claus, Walter Stechele
2006 2006 IEEE International Conference on Field Programmable Technology  
Although naturally belonging to the user process, hardware parts of codesigned reconfigurable applications execute outside of the operating system (OS) process: they have neither unified memory abstraction  ...  To prove our concept in practice and demonstrate the ease of programming, we execute image processing and cryptography applications on reconfigurable systems-on-chip running GNU/Linux that supports virtual  ...  ACKNOWLEDGEMENTS We acknowledge the help and support provided by Ingmar Cramm, Sven Gowal, Chidamber Kulkarni, Florian Mueller, Taranbir Singh, Jian Wang and the Xilinx University Program.  ... 
doi:10.1109/fpt.2006.270312 dblp:conf/fpt/VuleticICS06 fatcat:twl3d6d7gvaztexhki6arxvxgi

Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems

Joao Bispo, Nuno Paulino, Cardoso, Ferreira
2013 IEEE Transactions on Industrial Informatics  
This paper presents a novel approach to accelerate program execution by mapping repetitive traces of executed instructions, called Megablocks, to a runtime reconfigurable array of functional units.  ...  An offline tool suite extracts Megablocks from microprocessor instruction traces and generates a Reconfigurable Processing Unit (RPU) tailored for the execution of those Megablocks.  ...  of FUs; • Completely transparent use of the reconfigurable array of FUs at runtime using an unmodified CPU; • Implementation of a fully-functional hardware prototype using a MicroBlaze [6] as CPU on  ... 
doi:10.1109/tii.2012.2235844 fatcat:vhk62w4htvclvoka7ccovpmuw4

Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs

Alfonso Rodrıguez, Juan Valverde, Eduardo de la Torre
2015 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)  
ARTICo 3 is an architecture that permits to dynamically set an arbitrary number of reconfigurable hardware accelerators, each containing a given number of threads fixed at design time according to High  ...  Experimental results show OpenCL model compliance using multithreaded hardware accelerators and enhanced dynamic adaptation capabilities.  ...  ACKNOWLEDGMENTS The authors would like to thank the Spanish Ministry of Education, Culture and Sport for its support under the FPU grant program.  ... 
doi:10.1109/reconfig.2015.7393297 dblp:conf/reconfig/RodriguezVT15 fatcat:4fuztvso75amromc4xwv3d2ubq

Toward a runtime system for reconfigurable computers: A virtualization approach

M. Sabeghi, K. Bertels
2009 2009 Design, Automation & Test in Europe Conference & Exhibition  
In this paper we propose a virtualization layer to handle the program execution on reconfigurable computers in order to address one of their biggest problems which is the management of the reconfigurable  ...  reconfigurable hardware.  ...  The main advantage of reconfigurable computing is its ability to increase the performance with accelerated hardware execution, while possessing the flexibility of a software solution.  ... 
doi:10.1109/date.2009.5090915 dblp:conf/date/SabeghiB09 fatcat:rwihv3f2qvfrto4ar6qonnz7wm

Ecoscale: Reconfigurable Computing And Runtime System For Future Exascale Systems

Iakovos Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Dimitrios Nikolopoulos, Dirk Koch, John Goodacre, Ioannis Sourdis, Vassilis Papaefstathiou, Marcello Coppola, Manuel Palomino
2016 Zenodo  
The architecture supports shared partitioned reconfigurable resources accessed by any Worker in a PGAS partition, as well as automated hardware synthesis of these resources from an OpenCL-based programming  ...  To further increase energy efficiency, as well as to provide resilience, the Workers employ reconfigurable accelerators mapped into the virtual address space utilizing a dual stage System Memory Management  ...  The advantage of such systems is that they can accelerate particular applications by mapping (parts of) them to reconfigurable hardware, substantially improving execution time and energy efficiency.  ... 
doi:10.5281/zenodo.34893 fatcat:ocwfndo4vjei3hqucmndj22xu4

Transparent hardware synthesis of Java for predictable large-scale distributed systems [article]

Ian Gray, Yu Chan, Jamie Garside, Neil Audsley, Andy Wellings
2015 arXiv   pre-print
An important focus of this work is to make the use of FPGAs transparent though runtime co-design and partial reconfiguration.  ...  Initial results show that the use of Java does not hamper hardware generation, and provides tight execution time estimates.  ...  totally transparent FPGA acceleration through the use of online configuration and partial dynamic reconfiguration.  ... 
arXiv:1508.07142v1 fatcat:izfnahdd5zasnbt7tvrskj722u

A Position on Transparent Reconfigurable Systems

Luís Miguel Sousa, Nuno Paulino, João Canas Ferreira
2021 Zenodo  
In this paper, we propose a runtime mechanism for automatic reconfigurable resource management that will enable a hypothetical flow for combined hardware and software compilation.  ...  As these systems become increasingly complex, manual tuning and management of these heterogeneous resources becomes unfeasible.  ...  Furthermore, since silicon area is expensive [2] , the use of Hardware Accelerators (HwAs) is only justified under certain conditions.  ... 
doi:10.5281/zenodo.4728034 fatcat:3nohrd7o6fdwdo6notu2y5765u

Invited paper: Acceleration of computationally-intensive kernels in the reconfigurable era

Kyprianos Papadimitriou, Charalampos Vatsolakis, Dionisios Pnevmatikatos
2012 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)  
One of the major topics that attracts constantly the interest of research community is the acceleration of computationally-intensive applications.  ...  Present paper discusses problems in using reconfigurable technology and suggests some research directions.  ...  hardware should remain transparent to the user.  ... 
doi:10.1109/recosoc.2012.6322874 dblp:conf/recosoc/PapadimitriouVP12 fatcat:t22af7exkrckzkavou5teipvgi

Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration

Alfonso Rodriguez, Juan Valverde, Eduardo de la Torre, Teresa Riesgo
2014 2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)  
The inherent and explicit application-level parallelism of multithreaded CUDA kernels is used to generate hardware accelerators that act as thread blocks.  ...  execution is scheduled using a multiobjective optimization algorithm.  ...  Parallel-Processing Hardware Generation After almost twenty years of latent activity, HLS tools are now a feasible alternative to generate specific hardware using high-level programming languages.  ... 
doi:10.1109/recosoc.2014.6861363 dblp:conf/recosoc/RodriguezVTR14 fatcat:yqn2bj3gcvd3tlipujnivlca5e

ReconOS: An Operating System Approach for Reconfigurable Computing

Andreas Agne, Markus Happe, Ariane Keller, Enno Lubbers, Bernhard Plattner, Marco Platzner, Christian Plessl
2014 IEEE Micro  
hardware accelerators.  ...  Still, reconfigurable computing applications are rarely mapped exclusively to the FPGA accelerator.  ...  From the perspective of an application, it is thus completely transparent whether a thread is executing in software or hardware.  ... 
doi:10.1109/mm.2013.110 fatcat:k5pk2ntw2zfypi4x7zait2x4lm
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