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Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units
2013
International Journal of Reconfigurable Computing
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The ability to map instructions running in a microprocessor to a reconfigurable processing unit (RPU), acting as a coprocessor, enables the runtime acceleration of applications and ensures code and possibly ...
In this work, we focus on the mapping of loop-based instruction traces (called Megablocks) to RPUs. ...
mapped to DIM Detect repeating patterns of instructions in the execution trace and migrate those loops to an RPU Coupling Loose RPU/GPP coupling, shared instruction and data memory Tight RPU coupling ...
doi:10.1155/2013/340316
fatcat:nyypx6imyvcinksmma7rvv7ksa
Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)
2013
International Journal of Reconfigurable Computing
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We would like to thank all the reviewers for their valuable time and effort in the review process, and to provide constructive feedbacks to authors. ...
We hope that you will find in this special issue a valuable source of information to your future research. ...
Finally, one paper is within the area of reconfiguration techniques. In "Transparent runtime migration of loop-based traces of processor instructions to reconfigurable processing units," J. ...
doi:10.1155/2013/597323
fatcat:l3v7jtnc5fcsthqi7zluutdnqa
Architecture for Transparent Binary Acceleration of Loops with Memory Accesses
[chapter]
2013
Lecture Notes in Computer Science
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This paper presents an extension to a hardware/software system architecture in which repetitive instruction traces, called Megablocks, are accelerated by a Reconfigurable Processing Unit (RPU). ...
Switching between hardware and software execution is done transparently, without modifications to source code or executable binaries. ...
Conclusion This paper presented a general-purpose computing architecture based on a General Purpose Processor (GPP) and a Reconfigurable Processing Unit (RPU) automatically generated offline from instruction ...
doi:10.1007/978-3-642-36812-7_12
fatcat:p4kifbrcmngerorcyu3jotyx7q
Low-Complexity Online Synthesis for AMIDAR Processors
2010
International Journal of Reconfigurable Computing
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Thus, we believe that online synthesis that takes place during the execution of an application is one way to broaden the applicability of reconfigurable architectures. ...
Reconfigurable logic has often been promoted as a solution to these problems. Today, it can be found in two varieties: field programmable gate arrays or coarse-grained reconfigurable arrays. ...
Thus, the process of creating new functional units is transparent to the processor. Hence, a runtime prediction is not possible yet. ...
doi:10.1155/2010/953693
fatcat:peb7ybgujjcjjegwb7o2ualsau
Supporting runtime reconfigurable VLIWs cores through dynamic binary translation
2018
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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To preserve the single ISA programming model, we resort to Dynamic Binary Translation, and use this technique to enable dynamic code specialization for Runtime Reconfigurable VLIWs cores. ...
Such architectures combine Out of Order cores with smaller in-order ones to offer different power/energy profiles. ...
inter-block transformations are performed to merge blocks, build traces 3 and unroll loops. ...
doi:10.23919/date.2018.8342160
dblp:conf/date/RokickiRD18
fatcat:g5hf657vx5b3xb736kmwnf4fi4
DeSyRe: On-demand system reliability
2013
Microprocessors and microsystems
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In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. ...
This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. ...
To one extent, the Middleware makes all its actions transparent to the Runtime system in order to provide well-functioning hardware; that is in order to ensure the reconfiguration process is performed ...
doi:10.1016/j.micpro.2013.08.008
fatcat:jg623r4hmngthk652u7qi6ibme
Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support
2014
2014 IEEE International Symposium on Parallel and Distributed Processing with Applications
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This paper presents a binary acceleration approach based on extending a General Purpose Processor (GPP) with a Reconfigurable Processing Unit (RPU), both sharing an external data memory. ...
In this approach repeating sequences of GPP instructions are migrated to the RPU. The RPU resources are selected and organized off-line using execution trace information. ...
Our previous work presented a binary acceleration approach in which the execution of frequently executed loops is transparently migrated at run-time to a Reconfigurable Processing Unit (RPU), a tailored ...
doi:10.1109/ispa.2014.29
dblp:conf/ispa/PaulinoFC14
fatcat:u3mcgsqss5cf5lzno7pzbustga
A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses
2014
ACM Transactions on Reconfigurable Technology and Systems
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A Reconfigurable Processing Unit (RPU) is used as a coprocessor of the General Purpose Processor (GPP) to accelerate the execution of repetitive instruction sequences called Megablocks. ...
A toolchain detects Megablocks from instruction traces and generates customized RPU implementations. ...
The WARP processor is a MicroBlaze-based system that is able to migrate the innermost loops to an FPGA-based reconfigurable logic fabric connected to the MicroBlaze [Lysecky and Vahid 2009]. ...
doi:10.1145/2629468
fatcat:eogxo4p4yrb4tdehmgfxa7yvra
Reconfigurable Acceleration with Binary Compatibility for General Purpose Processors
[chapter]
2009
IFIP International Federation for Information Processing
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Based on all these facts, this work proposes a new Binary Translation algorithm, implemented in hardware and working in parallel to the processor, responsible for transforming sequences of instructions ...
Therefore, we can take advantage of using pure combinational logic to optimize even control-flow oriented code in a totally transparent process, without any modification in the source code or binary. ...
of instructions at run time to be executed on a reconfigurable array, in a totally transparent process: there is no necessity of changing the code before its execution at all. ...
doi:10.1007/978-0-387-89558-1_15
fatcat:njmcai5ndfgwvkkn6lgflczp3y
Analyzing Behavior Specialized Acceleration
2016
ACM SIGOPS Operating Systems Review
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For example, a 2-wide OOO processor with three BSAs matches the performance of a conventional 6-wide OOO core, has 40% lower area, and is 2.6× more energy efficient. ...
To study the potential of BSAs, we propose a novel modeling technique called the Transformable Dependence Graph (TDG) -a higher level alternative to the time-consuming traditional compiler+simulator approach ...
At run-time, depending on the affinity of the code, the execution may migrate to one of the BSAs, a process which is transparent to the programmer. ...
doi:10.1145/2954680.2872412
fatcat:66uy7l3ggbh6ze2mp33wtgmbtm
Message from the Organizers
2012
2012 Third Workshop on Applications for Multi-Core Architecture
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We suggest that schedulers designed with an understanding of the requirements of all process classes and their mixes, as well the abilities of the underlying architecture, might be the solution to this ...
Specifically, we are interested in parallel process scheduling, which has been a topic of significant study in the supercomputing community, but so far little of this research has trickled down to the ...
ACKNOWLEDGEMENTS We would like to thank the Xilinx University Program for its valuable help on partial reconfiguration and its hardware and software donations. ...
doi:10.1109/wamca.2012.4
fatcat:weftcii3gnfdrcgqqhop72muqq
Message from Organizers
2015
2015 Third International Symposium on Computing and Networking (CANDAR)
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We suggest that schedulers designed with an understanding of the requirements of all process classes and their mixes, as well the abilities of the underlying architecture, might be the solution to this ...
Specifically, we are interested in parallel process scheduling, which has been a topic of significant study in the supercomputing community, but so far little of this research has trickled down to the ...
ACKNOWLEDGEMENTS We would like to thank the Xilinx University Program for its valuable help on partial reconfiguration and its hardware and software donations. ...
doi:10.1109/candar.2015.4
fatcat:fcvejkemfjaczbcxgjrviru3pu
Message from the Organizers
2007
Fourth International Workshop on Model-Based Methodologies for Pervasive and Embedded Software (MOMPES'07)
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We suggest that schedulers designed with an understanding of the requirements of all process classes and their mixes, as well the abilities of the underlying architecture, might be the solution to this ...
Specifically, we are interested in parallel process scheduling, which has been a topic of significant study in the supercomputing community, but so far little of this research has trickled down to the ...
ACKNOWLEDGEMENTS We would like to thank the Xilinx University Program for its valuable help on partial reconfiguration and its hardware and software donations. ...
doi:10.1109/mompes.2007.11
fatcat:xxlvjyydibg53oonip25ubnz4q
Message from the Organizers
2008
2008 5th International Workshop on Model-based Methodologies for Pervasive and Embedded Software
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We suggest that schedulers designed with an understanding of the requirements of all process classes and their mixes, as well the abilities of the underlying architecture, might be the solution to this ...
Specifically, we are interested in parallel process scheduling, which has been a topic of significant study in the supercomputing community, but so far little of this research has trickled down to the ...
ACKNOWLEDGEMENTS We would like to thank the Xilinx University Program for its valuable help on partial reconfiguration and its hardware and software donations. ...
doi:10.1109/mompes.2008.4
fatcat:ctsxrgwiibd5fcgvenehisljs4
Message from the Organizers
2012
2012 Third International Conference on Networking and Computing
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We suggest that schedulers designed with an understanding of the requirements of all process classes and their mixes, as well the abilities of the underlying architecture, might be the solution to this ...
Specifically, we are interested in parallel process scheduling, which has been a topic of significant study in the supercomputing community, but so far little of this research has trickled down to the ...
ACKNOWLEDGEMENTS We would like to thank the Xilinx University Program for its valuable help on partial reconfiguration and its hardware and software donations. ...
doi:10.1109/icnc.2012.5
fatcat:mmkxzhoj2fbctfhufxjeepr6jm
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