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Translation Validation for Clock Transformations in a Synchronous Compiler [chapter]

Van Chan Ngo, Jean-Pierre Talpin, Thierry Gautier, Paul Le Guernic
<span title="">2015</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
In this work, we adopt this approach to construct a validator that formally verifies the preservation of clock semantics during the Signal compiler transformations.  ...  Translation validation was introduced as a technique to formally verify the correctness of code generators that attempts to ensure that program transformations preserve the semantics of input program.  ...  Clock Model Translation Validation We adopt the translation validation approach [20, 21] to formally verify that the clock semantics is preserved for every transformation of the compiler.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-662-46675-9_12">doi:10.1007/978-3-662-46675-9_12</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/sn3daagttje6djniu23gartsaq">fatcat:sn3daagttje6djniu23gartsaq</a> </span>
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Modular translation validation of a full-sized synchronous compiler using off-the-shelf verification tools

Van-Chan Ngo, Jean-Pierre Talpin, Thierry Gautier, Loïc Besnard, Paul Le Guernic
<span title="">2015</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/iriutb7bwvgxtirzvmsmxfdqui" style="color: black;">Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems - SCOPES &#39;15</a> </i> &nbsp;
This methodology results from the ANR project VERISYNC, in which we aimed at revisiting Pnueli's seminal work on translation validation using off-the-shelf, up-to-date, verification technology.  ...  In face of the enormous task at hand, the verification of a compiler infrastructure comprising around 500 000 lines of C code, we devised to narrow down and isolate the problem to the very data-structures  ...  ] proposed a framework for translation validation.  ... 
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Formal verification of synchronous data-flow program transformations toward certified compilers

Van Chan Ngo, Jean-Pierre Talpin, Thierry Gautier, Paul Le Guernic, Loïc Besnard
<span title="2013-09-13">2013</span> <i title="Springer Nature"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/mea4bx5mifbxdbgjmmfhl6qbhq" style="color: black;">Frontiers of Computer Science</a> </i> &nbsp;
Translation validation is implemented for every compilation phase from the initial phase until the latest phase where the executable code is generated, by proving that the transformation in each phase  ...  Translation validation was introduced in the 90's by Pnueli et al. as a technique to formally verify the correctness of code generators.  ...  Acknowledgements We would like to thank Sandeep Shukla for his early interest and enthusiasm, and Abdoulaye Gamatié, Laure Gonnord for discussing some parts of this work and exchanging ideas.  ... 
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Formal Verification of Compiler Transformations on Polychronous Equations [chapter]

Van Chan Ngo, Jean-Pierre Talpin, Thierry Gautier, Paul Le Guernic, Loïc Besnard
<span title="">2012</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
In this paper, adopting the translation validation approach, we present a formal verification process to prove the correctness of compiler transformations on systems of polychronous equations.  ...  In this paper, the highly optimizing, industrial compiler from the synchronous language SIGNAL to C is addressed.  ...  In this paper, adopting the translation validation approach in [15] , we present an automated verification process to prove the correctness of a multi-clocked synchronous language compiler.  ... 
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Translation Validation for Synchronous Data-Flow Specification in the SIGNAL Compiler [chapter]

Van Chan Ngo, Jean-Pierre Talpin, Thierry Gautier
<span title="">2015</span> <i title="Springer International Publishing"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
Translation Validation for Synchronous Data-Flow Specification in the SIGNAL Compiler.  ...  Translation Validation for Synchronous Data-Flow Specification in the SIGNAL Compiler Van Chan Ngo, Jean-Pierre Talpin, Thierry Gautier To cite this version: Van Introduction Motivation A compiler  ... 
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Translation Validation: From DC+ to C [chapter]

A. Pnueli, O. Shtrichman, M. Siegel
<span title="">1999</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
In this paper we demonstrate the feasibility of tremslation vcilidation for industrial code generators from DC-|--a widely used intermediate format for synchronous languages-to C.  ...  Rather than proving in advance that the compiler always produces a target code which correctly implements the source code (compiler verification), each individual translation (i.e. a run of the compiler  ...  In this paper we consider translation validation for synchronous languages.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/3-540-48257-1_8">doi:10.1007/3-540-48257-1_8</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/qaqo5l6n3bfrlfuort4jhghxae">fatcat:qaqo5l6n3bfrlfuort4jhghxae</a> </span>
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Towards a verified compiler prototype for the synchronous language SIGNAL

Zhibin Yang, Jean-Paul Bodeveix, Mamoun Filali, Kai Hu, Yongwang Zhao, Dianfu Ma
<span title="2015-11-11">2015</span> <i title="Springer Nature"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/mea4bx5mifbxdbgjmmfhl6qbhq" style="color: black;">Frontiers of Computer Science</a> </i> &nbsp;
This paper reports a compiler prototype for SIGNAL.  ...  Compared with the existing SIGNAL compiler, we propose a new intermediate representation (named S-CGA, a variant of clocked guarded actions), to integrate more synchronous programs into our compiler prototype  ...  However, translation validation treats the compiler as a "black box", namely it just checks the input and output of each program transformation to validate the semantics preservation.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/s11704-015-4364-y">doi:10.1007/s11704-015-4364-y</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/7x6wchqztrfmpassc3ip7eres4">fatcat:7x6wchqztrfmpassc3ip7eres4</a> </span>
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Towards SMV Model Checking of Signal (multi-clocked) Specifications

Julio C. Peralta, Thierry Gautier
<span title="2009-12-17">2009</span> <i title="European Association of Software Science and Technology"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ds6dyxrqzrddpmxtwf2p5ljfn4" style="color: black;">Electronic Communications of the EASST</a> </i> &nbsp;
SMV, in turn, is a language and model checker where synchronous models are single-clocked by definition.  ...  In particular, we propose a translation from possibly multi-clocked Signal specifications into SMV specifications for their corresponding verification by model checking.  ...  This expression was not translated as a clock definition since the SIGNAL compiler was unable to verify its validity, hence its form of constraint rather than a directed assignment (as those appearing  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.14279/tuj.eceasst.23.308">doi:10.14279/tuj.eceasst.23.308</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/journals/eceasst/PeraltaG09.html">dblp:journals/eceasst/PeraltaG09</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/2xff6xaqgnfdhjzavqd3bxxldq">fatcat:2xff6xaqgnfdhjzavqd3bxxldq</a> </span>
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Dependent Types for Multi-Rate Flows in Synchronous Programming

William Blair, Hongwei Xi
<span title="2017-02-07">2017</span> <i title="Open Publishing Association"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qzezkwolyvf33pglm2jldjklca" style="color: black;">Electronic Proceedings in Theoretical Computer Science</a> </i> &nbsp;
Synchronous programming languages emerged in the 1980s as tools for implementing reactive systems, which interact with events from physical environments and often must do so under strict timing constraints  ...  In this report, we encode inside ATS various real-time primitives in an experimental synchronous language called Prelude, where ATS is a statically typed language with an ML-like functional core that supports  ...  (a, SFlow(a, n, p) ) → SFlow(a, n, p) Figure 3: Some clock transformation operators and their types The clock transformation operators in Prelude are to be translated into regular functions in ATS.  ... 
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Verified Lustre Normalization with Node Subsampling

Timothy Bourke, Paul Jeanmaire, Basile Pesin, Marc Pouzet
<span title="2021-10-31">2021</span> <i title="Association for Computing Machinery (ACM)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/3yu4mbaainhw5gol4yayc35pfe" style="color: black;">ACM Transactions on Embedded Computing Systems</a> </i> &nbsp;
Lustre and Scade are dataflow languages for programming embedded systems. Dataflow programs are compiled by a succession of passes.  ...  The generalization of node inputs requires adding a compiler pass to ensure the initialization of variables passed in function calls.  ...  Brun for his many contributions to the Vélus compiler, J.-L. Colaço for his explanations about Scade, X. Leroy for his explanations and advice on CompCert, and A. Guatto for his suggestions.  ... 
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Automated translation of C/C++ models into a synchronous formalism

H. Kalla, J.-P. Talpin, D. Berner, L. Besnard
<span title="">2006</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/okxd7mlvqvf7nhme7j7uxozfqm" style="color: black;">13th Annual IEEE International Symposium and Workshop on Engineering of Computer-Based Systems (ECBS&#39;06)</a> </i> &nbsp;
Validating that reused components are properly connected to each other and function correctly has become a major issue for such designs and requires the use of formal methods.  ...  The C/C++ into SIGNAL transformation process is performed in two steps.  ...  As in [1, 2, 19, 21, 20] , we use the synchronous approach to validate system designs.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ecbs.2006.27">doi:10.1109/ecbs.2006.27</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/ecbs/KallaTBB06.html">dblp:conf/ecbs/KallaTBB06</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/s5ndylbxfvc6rmk45e44d5pqvu">fatcat:s5ndylbxfvc6rmk45e44d5pqvu</a> </span>
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LTSs for translation validation of (multi-clocked) SIGNAL specifications

Julio C. Peralta, Thierry Gautier, Loic Besnard, Paul Le Guernic
<span title="">2010</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/u6xokkbfobfg7ogddh3jc7mgja" style="color: black;">Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010)</a> </i> &nbsp;
In general, this guarantee takes either the form of a certified compiler, or the validation of each translation. Here we adopt the translation validation approach.  ...  Design of critical embedded systems demands for guarantees on the reliability of the implementation/compilation of a specification.  ...  , and as a compile time code manipulation/transformation.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/memcod.2010.5558632">doi:10.1109/memcod.2010.5558632</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/memocode/PeraltaGBG10.html">dblp:conf/memocode/PeraltaGBG10</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/gzmd7g7lorgyviexoxiedmpxia">fatcat:gzmd7g7lorgyviexoxiedmpxia</a> </span>
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Clock-directed modular code generation for synchronous data-flow languages

Dariusz Biernacki, Jean-Louis Colaço, Gregoire Hamon, Marc Pouzet
<span title="">2008</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/6dcohyzfhveypik7x4entpurlu" style="color: black;">Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems - LCTES &#39;08</a> </i> &nbsp;
Such a formalization is now fundamental in the long-term goal to develop a mathematically certified compiler for a synchronous language as well as in simplifying existing implementations.  ...  This article presents in full detail the modular compilation of synchronous block diagrams into sequential code.  ...  Acknowledgments We thank the anonymous reviewers for their helpful comments.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1375657.1375674">doi:10.1145/1375657.1375674</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/lctrts/BiernackiCHP08.html">dblp:conf/lctrts/BiernackiCHP08</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/izx3wpz7lrc4lmf4yiksk72gha">fatcat:izx3wpz7lrc4lmf4yiksk72gha</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170810160416/http://www.ii.uni.wroc.pl/~dabi/publications/LCTES08/biernacki-al-lctes08.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/47/98/47981a95074cbea3675b76b6fb1f12f856d872e9.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1375657.1375674"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Clock-directed modular code generation for synchronous data-flow languages

Dariusz Biernacki, Jean-Louis Colaço, Gregoire Hamon, Marc Pouzet
<span title="2008-06-27">2008</span> <i title="Association for Computing Machinery (ACM)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/xu5bk2lj5rbdxlx6222nw7tsxi" style="color: black;">SIGPLAN notices</a> </i> &nbsp;
Such a formalization is now fundamental in the long-term goal to develop a mathematically certified compiler for a synchronous language as well as in simplifying existing implementations.  ...  This article presents in full detail the modular compilation of synchronous block diagrams into sequential code.  ...  Acknowledgments We thank the anonymous reviewers for their helpful comments.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1379023.1375674">doi:10.1145/1379023.1375674</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/bxalvxiyindspahuzkbfnnjgu4">fatcat:bxalvxiyindspahuzkbfnnjgu4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170810160416/http://www.ii.uni.wroc.pl/~dabi/publications/LCTES08/biernacki-al-lctes08.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/47/98/47981a95074cbea3675b76b6fb1f12f856d872e9.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1379023.1375674"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Hardware Synthesis Using SAFL and Application to Processor Design [chapter]

Alan Mycroft, Richard Sharp
<span title="">2001</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
We survey the work done so far in the FLaSH project (Functional Languages for Synthesising Hardware) in which the core ideas are (i) using a functional language SAFL to describe hardware computation; (  ...  ii) transforming SAFL programs using various meaning-preserving transformations to choose the area-time position (e.g. by resource duplication/sharing, specialisation, pipelining); and (iii) compiling  ...  This work was supported by (UK) EPSRC grant GR/ N64256 "A Resource-Aware Functional Language for Hardware Synthesis"; the second author was also sponsored by AT&T Research Laboratories Cambridge.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/3-540-44798-9_2">doi:10.1007/3-540-44798-9_2</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/hgrmjts2c5dzdcs6c54csjdvru">fatcat:hgrmjts2c5dzdcs6c54csjdvru</a> </span>
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