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A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size

S. Natarajan, M. Agostinelli, S. Akbar, M. Bost, A. Bowonder, V. Chikarmane, S. Chouksey, A. Dasgupta, K. Fischer, Q. Fu, T. Ghani, M. Giles (+40 others)
2014 2014 IEEE International Electron Devices Meeting  
The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4 th generation high-k metal gate, and 6 th -generation strained silicon, resulting in the highest drive currents yet reported  ...  for 14nm technology.  ...  KEY DESIGN RULES & TECHNOLOGY FEATURES TRANSISTOR PERFORMANCE AND VARIATION Lgate scaling from 26nm in the 22nm node (from conference presentation from [1] ) to 20nm in the 14nm node is enabled by fin  ... 
doi:10.1109/iedm.2014.7046976 fatcat:xo43o3k7qndoleb5kllloaczre

A comparative study of reliability for finfet

Saleh Shaheen, Gady Golan, Moshe Azoulay, Joseph Bernstein
2018 Facta universitatis - series Electronics and Energetics  
As such, the reliability physics of FinFET was modified in order to fit the newly developed transistor technology.  ...  This paper highlights the roles and impacts of these various effects and aging mechanisms on FinFET transistors compared to planar transistors on the basic approach of the physics of failure mechanisms  ...  Acknowledgement: Sponsored by US Dept. of Defense (ONR and AFOSR).  ... 
doi:10.2298/fuee1803343s fatcat:rjyajmi2dzfc5ciw5mpaqqp4vm

Aging Degradation Impact on the Stability of 6T-SRAM Bit-cell

S. K. Koushik, B. Lakshmi
2015 Indian Journal of Science and Technology  
Reliability is mainly due to aging degradation which characterises BTI (Bias Temperature Instability) and HCI (Hot Carrier Injection) resulting in permanent damage to MOS parameters and as a result MOS  ...  In present technology nodes reliability is a growing concern where the static SRAM memories are not able to store the contents for a longer period of time.  ...  Also special thanks to my friends at ARM who made my work easier and more interesting by stating in enthusiastic problems which made the work really phenomenal also.  ... 
doi:10.17485/ijst/2015/v8i20/77734 fatcat:lmpqvyfrwraj5igphaesuduszm

Understanding CMOS Technology Through TAMTAMS Web

Fabrizio Riente, Izhar Hussain, Massimo Ruo Roch, Marco Vacca
2016 IEEE Transactions on Emerging Topics in Computing  
INTRODUCTION T HE foundation of the "Digital Age", the period of history in which we live, lies deeply in the MOS-FET (metal-oxide-semiconductor field effect transistor) technology.  ...  To be effective as a teaching instrument, it is not sufficient for a tool to simply provide a good and reliable analysis, it must also exploit the potential of the "Digital Age".  ... 
doi:10.1109/tetc.2015.2488899 fatcat:fc2puncm6jhofka3majwjlg3cq

A Survey of Aging Monitors and Reconfiguration Techniques [article]

Leonardo Rezende Juracy, Matheus Trevisan Moreira, Alexandre de Morais Amory, Fernando Gehm Moraes
2020 arXiv   pre-print
CMOS technology scaling makes aging effects an important concern for the design and fabrication of integrated circuits.  ...  Aging deterioration reduces the useful life of a circuit, making it fail earlier. This deterioration can affect all portions of a circuit and impacts its performance and reliability.  ...  ., from Intel, [13] , tri-gate technologies as 14nm can help to mitigate HCI effects toghter with body bias adjust techniques.  ... 
arXiv:2007.07829v1 fatcat:2syuq4acm5ci3kafbxljvzbguq

Design for manufacturability and reliability in extreme-scaling VLSI

Bei Yu, Xiaoqing Xu, Subhendu Roy, Yibo Lin, Jiaojiao Ou, David Z. Pan
2016 Science China Information Sciences  
In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI.  ...  However, as the transistor feature size is further shrunk to sub-14nm nanometer regime, modern integrated circuit (IC) designs are challenged by exacerbated manufacturability and reliability issues.  ...  Acknowledgements This work was supported in part by US National Science Foundation, Semiconductor Research Corporation, National Natural Science Foundation of China, TOSHIBA, and CUHK Direct Grant for  ... 
doi:10.1007/s11432-016-5560-6 fatcat:lz5ebjqeprbanbkgxqxjeouip4

Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips

Sriram Vangal, Somnath Paul, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, James Tschanz, Vivek De
2020 Journal of Low Power Electronics and Applications  
We discuss application of NTV design techniques, necessary for reliable operation over a wide supply voltage range—from nominal down to the NTV regime, and for a variety of IPs.  ...  Evaluation results spanning Intel's 32-, 22- and 14-nm CMOS technologies across four test chips are presented, confirming substantial energy benefits that scale well with Moore's law.  ...  The 14-nm NTV-WSN design uses HP, standard-performance (SP), ULP, and thick-gate (TG)-all four transistor families in 14-nm second-generation tri-gate SoC platform technology [14] .  ... 
doi:10.3390/jlpea10020016 fatcat:wuwirnk4ljc7tjllpzc3ng7jei

DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors [article]

Jawad Haj Yahya, Jeremie S. Kim, A. Giray Yaglikci, Jisung Park, Efraim Rotem, Yanos Sazeides, Onur Mutlu
2021 arXiv   pre-print
To reduce the leakage power of inactive (dark) silicon components, modern processor systems shut-off these components' power supply using low-leakage transistors, called power-gates.  ...  In addition, DarkGates fulfills the requirements of the ENERGY STAR and the Intel Ready Mode energy efficiency benchmarks of desktop systems.  ...  ., “Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate Tolerance,” JSSC, 2008. tri-gate CMOS,” in CICC, 2015.  ... 
arXiv:2112.11587v1 fatcat:snli37hdubdjfbt553znhtw33q

State-of-the-Art and Trends for Computing and Interconnect Network Solutions for HPC and AI

A. Tekin, A.Tuncer Durak, C. Piechurski, D. Kaliszan, F. Aylin Sungur, F. Robertsén, P. Gschwandtner
2021 Zenodo  
) and interconnect capabilities and provides an outlook on future trends in terms of mid-term projections about what users may expect in the coming years.  ...  Since 2000, High Performance Computing (HPC) resources have been extremely homogeneous in terms of underlying processors technologies.  ...  Acknowledgements This work was financially supported by the PRACE project funded in part by the EU's Horizon 2020 Research and Innovation programme (2014-2020) under grant agreement 823767.  ... 
doi:10.5281/zenodo.5717283 fatcat:irgzrdxr6ncijcfxsdb3sdodii

Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs

Alexandra Kourfali, David Merodio Codinachs, Dirk Stroobandt
2017 2017 17th European Conference on Radiation and Its Effects on Components and Systems (RADECS)  
Impact of negative back gate bias to transistor parameter degradation is investigated. An improved back gate compensated strategy is proposed.  ...  Charge trapping in high-K dielectrics in Si-based and alternative-channel devices will be briefly reviewed, with an emphasis on effects in advanced gate stacks and emerging nanoscale technologies.  ...  We perform a reliability and performance analysis of hardware and software co-designs in APSoCs.  ... 
doi:10.1109/radecs.2017.8696242 fatcat:frcrfuza2fdstitbsjoda5sn4y

State-of-the-Art and Trends for Computing and Interconnect Network Solutions for HPC and AI

A. Tekin, A.Tuncer Durak, C. Piechurski, D. Kaliszan, F. Aylin Sungur, F. Robertsén, P. Gschwandtner
2021 Zenodo  
) and interconnect capabilities and provides an outlook on future trends in terms of mid-term projections about what users may expect in the coming years.  ...  Since 2000, High Performance Computing (HPC) resources have been extremely homogeneous in terms of underlying processors technologies.  ...  Acknowledgements This work was financially supported by the PRACE project funded in part by the EU's Horizon 2020 Research and Innovation programme (2014-2020) under grant agreement 823767.  ... 
doi:10.5281/zenodo.5534079 fatcat:fdknu7w4mfc5foa4gnmt5vqdna

Microelectronics packaging technology roadmaps, assembly reliability, and prognostics

Reza Ghaffarian
2016 Facta universitatis - series Electronics and Energetics  
The paper also summarizes the findings of numerous articles and websites that allotted to the emerging and trends in microelectronics packaging technologies.  ...  Due to the breadth of work being performed in this field, this paper presents only a number of key packaging technologies.  ...  Acknowledgments: The research described in this publication is being conducted at the Jet  ... 
doi:10.2298/fuee1604543g fatcat:3azhhqsxufa7vbzdh5twk557xi

Nanofabrication for Molecular Scale Devices [chapter]

Susmit Kumar, Shilpi Karmakar, Alessandro Bramanti, Ross Rinaldi, Giuseppe Maruccio
2011 Nanofabrication  
Whereas, Intel in 2011 has launched its 22nm node transistors called the tri-gate transistor Doyle et al., 2003) which uses conventional fabrication tools.  ...  transistors but requiring the growth and placing of one crystal per transistor separately, which is the bottle-neck of this technology.  ... 
doi:10.5772/28491 fatcat:qmxl5mdapzajrfwtbuuvl5ioyi

Program

2021 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)  
The fully integrated oscillator is based on a single HEMT transistor having a gate length of 70 nm and realized using a 2DEG in In 0.7 Ga 0.3 As. The chip area is about 0.3 mm 2 .  ...  It is shown that by magnetically coupling a pair of inductors connected at the gate and drain of a transistor, a loss-less (series-series) feedback path from the drain-current to the gate is generated  ...  This workshop will also cover several state-of-the-art technologies in wearable devices and in indoor localization in the context of low-power wireless communications.  ... 
doi:10.1109/rfic51843.2021.9490449 fatcat:wmoshjhq3nhxxljgu46qup325u

Defense Advanced Research Projects Agency (Darpa) Fiscal Year 2015 Budget Estimates

Department Of Defense Comptroller's Office
2014 Zenodo  
Included in this category is the National Center for Advancing Translational Sciences (NCATS) efforts to reengineer drug discovery and development in collaboration with industry, academia, the Food and  ...  Also cited under this heading is the proposed DARPA-like funding mechanism to stimulate technology development, which is detailed below.  ...  all performance goals in the presence of extreme process technology variations, and to sustain circuit performance in the field in the face of changing environmental conditions and component aging.  ... 
doi:10.5281/zenodo.1215345 fatcat:fjzhmynqjbaafk67q2ckcblj2m
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