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Transactional Memory Architecture and Implementation for IBM System Z
2012
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
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© 2012 IBM Corporation ...
Transactions
• Processor guarantees transaction will eventually
complete; no need for software fallback path
• Limitations (constraints) on types and number of
instructions and range of storage accesses ...
doi:10.1109/micro.2012.12
dblp:conf/micro/JacobiSG12
fatcat:ozqhx3pb3rfoxj5gpmchqsi66e
Robust architectural support for transactional memory in the power architecture
2013
Proceedings of the 40th Annual International Symposium on Computer Architecture - ISCA '13
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and the need for robustness beyond that of some early implementations. ...
We describe these interactions, the overall architecture, and discuss the motivation and rationale for our choices of architectural semantics, beyond what is typically found in reference manuals. ...
Acknowledgments The definition of this architecture was made possible by contributions from a wide group of IBMers. We would especially like to acknowledge Bob Blainey, Mary Brown, Susan Eisen, ...
doi:10.1145/2485922.2485942
dblp:conf/isca/CainMFMWL13
fatcat:yn4uooo6sbbu7kwaso3biiefu4
Robust architectural support for transactional memory in the power architecture
2013
SIGARCH Computer Architecture News
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and the need for robustness beyond that of some early implementations. ...
We describe these interactions, the overall architecture, and discuss the motivation and rationale for our choices of architectural semantics, beyond what is typically found in reference manuals. ...
Acknowledgments The definition of this architecture was made possible by contributions from a wide group of IBMers. We would especially like to acknowledge Bob Blainey, Mary Brown, Susan Eisen, ...
doi:10.1145/2508148.2485942
fatcat:5a57nba23fcxzoydwisggrmf7e
Decoupled access/execute computer architectures
1984
ACM Transactions on Computer Systems
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An architecture for high-performance scalar computation is proposed and discussed. The main feature of the architecture is a high degree of decoupling between operand access and execution. ...
This results in an implementation that has two separate instruction streams that communicate via architectural queues. ...
The IBM and Amdahl high-performance implementations of the System 360/ 370 architecture [1, 8] almost invariably decompose the design into an I-unit and an E-unit. ...
doi:10.1145/357401.357403
fatcat:bldhhclgifhjdeza2a2bgsxvne
MAINFRAME TO ENTERPRISE TO THE IS CURRICULUM
2012
Issues in Information Systems
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The growth and market penetration of IBM zEnterprise has been spectacular. This evolution of IBM Enterprise Systems provides many opportunities for IS/CS majors. ...
A case study implementing the IBM Academic Initiative in an ABET-CAC curriculum is presented. ...
IBM's LPAR architecture supports only z/OS, z/VM, and zLinux. z/OS is a full featured operating system, while z/VM is a hypervisor. ...
doi:10.48009/2_iis_2012_182-192
fatcat:i4kfnn3gofh7xe6lrbuwxhwroi
Transaction Security System
1991
IBM Systems Journal
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IBM SYSTEMS JOURNAL, VOL 30, NO 2, 1991 It was decided early that the Transaction Security System would faithfully implement the Common Cryptographic Architecture. ...
IBM SYSTEMS JOURNAL, VOL 30, NO 2, 1991 unique to the Transaction Security System are implemented. ...
doi:10.1147/sj.302.0206
fatcat:ddvoanefw5ayxi5d27ehlci2i4
A Smart Proxy for a Next Generation Web Services Transaction
2007
6th IEEE/ACIS International Conference on Computer and Information Science (ICIS 2007)
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In this paper, we propose and describe sProxy -smart proxy, a software tool in Web Services transaction. sProxy acts as a gateway between transaction management systems and Web Services which implements ...
a key abstraction of proxy management systems. ...
TPS
Main features
CICS (IBM)
CICS (Customer Information
Control System) is a transaction
server from IBM which runs on
mainframe systems under z/OS or
z/VSE. ...
doi:10.1109/icis.2007.44
dblp:conf/ACISicis/PradhanZ07
fatcat:qlnxawq6jfct5byhrmnb2hl6p4
Do C and Java programs scale differently on Hardware Transactional Memory?
2013
2013 IEEE International Symposium on Workload Characterization (IISWC)
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As commercial implementations of Hardware Transactional Memory (HTM) enter the market, the HTM support in two major programming languages, C and Java, is of critical importance to the industry. ...
We studied the scalability of the same transactional memory applications written in C and Java, using the STAMP benchmarks. We performed our HTM experiments on an IBM mainframe zEnterprise EC12. ...
ACKNOWLEDGMENT We would like to thank the members of the Commercial Systems group in IBM Research -Tokyo for helpful discussions. ...
doi:10.1109/iiswc.2013.6704668
dblp:conf/iiswc/OdairaCN13
fatcat:yk2d5o36praznoophrbpjizhnm
Near real-time analytics with IBM DB2 analytics accelerator
2013
Proceedings of the 16th International Conference on Extending Database Technology - EDBT '13
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Additionally, the Accelerator shields DB2 for z/OS as the transactional system from performance degradation caused by the analyt-...$15.00. ical workload and the replication component synchronizes all ...
The IBM DB2 Analytics Accelerator (IDAA) implements the vision of a universal relational DBMS that processes OLTP and analytical-type queries in a single system, but on two fundamentally different query ...
Figure 4 : 4 Screenshot of the IDAA Studio User Interface
Figure 5 : 5 Decision Tree that Proposes a
IBM PureData System for Analytics IBM PureData System for Analytics DB2 for z/OS
on IBM zEnterprise ...
doi:10.1145/2452376.2452444
dblp:conf/edbt/MartinKKI13
fatcat:jlrtnnsx6jhtlpfso2bs5oe67a
Decoupled access/execute computer architectures
1998
25 years of the international symposia on Computer architecture (selected papers) - ISCA '98
Preserved Fulltext
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An architecture for high-performance scalar computation is proposed and discussed. The main feature of the architecture is a high degree of decoupling between operand access and execution. ...
This results in an implementation that has two separate instruction streams that communicate via architectural queues. ...
The IBM and Amdahl high-performance implementations of the System 360/ 370 architecture [1, 8] almost invariably decompose the design into an I-unit and an E-unit. ...
doi:10.1145/285930.285982
dblp:conf/isca/Smith98d
fatcat:rerg34mrpjecpe32m74foppnwm
Decoupled access/execute computer architectures
1982
SIGARCH Computer Architecture News
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
An architecture for high-performance scalar computation is proposed and discussed. The main feature of the architecture is a high degree of decoupling between operand access and execution. ...
This results in an implementation that has two separate instruction streams that communicate via architectural queues. ...
The IBM and Amdahl high-performance implementations of the System 360/ 370 architecture [1, 8] almost invariably decompose the design into an I-unit and an E-unit. ...
doi:10.1145/1067649.801719
fatcat:rs7imhyh3fd53bzkn27kskr5cq
Java server benchmarks
2000
IBM Systems Journal
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The file type is application/pdf.
He has also worked on architecture and design in various system software areas for the IBM System/38 and AS/400 products. He holds nine issued patents. He received a B.S. degree in ...
We also present performance measurements and analysis from multiple IBM server platforms, including both uniprocessor and multiprocessor systems. ). Mr. ...
Acknowledgments We thank Ben Hoflich, Jimmy Dewitt, and Walter Fraser for helping us to run the benchmarks and graph the results.
Cited references ...
doi:10.1147/sj.391.0057
fatcat:kvycgojsmzcdljp5xsyazxbeye
Leveraging virtualization to optimize high-availability system configurations
2008
IBM Systems Journal
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Drawing on practical experiences from an IBM development test lab, this paper looks at how virtualization technologies, methodologies, and techniques can augment and amplify traditional HA approaches while ...
boundaries, and avoiding hazards that await the unwary. ...
Examples include the IBM* System z* Processor Resource/System Manager* (PR/SM*) hypervisor, and the IBM POWER Hypervisor* firmware. ...
doi:10.1147/sj.2008.5386515
fatcat:db6mpgmgu5e2jpkslh2mjgpxjm
Preface
1995
IBM Systems Journal
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The Internet Archive has digitized a microfilm copy of this work. It may be possible to borrow a copy for reading.
SYSTEMS JOURNAL, VOL 34, NO 2, 1995
distributed memory systems. ...
The architecture and execu- tion model of DB2 Parallel Edition provide pro- cessor and disk storage scalability, large database capacity, query optimization, execution time op- timization, favorable transaction ...
doi:10.1147/sj.342.0144
fatcat:o52yve5ckjczbnws27zazdoifq
Aligning technology and business: Applying patterns for legacy transformation
2005
IBM Systems Journal
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In this paper, we discuss techniques for accelerating change to legacy systems and for streamlining an application portfolio. ...
The paper describes how these techniques are applied to two stages of the software life cycle-initial analysis and detailed analysis-and summarizes experience gained from projects working with IBM clients ...
The transaction and master files are sorted on some common key. In the classic batch update program, an in-memory copy of the master file record is updated for each applicable transaction. ...
doi:10.1147/sj.441.0025
fatcat:etxb3es3brcyff2rzsvwcb2cne
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