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Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad Khellah, Shih-Lien Lu
2008 SIGARCH Computer Architecture News  
As big as possible when performance is important (high voltages).  Trades off cache capacity to allow low voltage when power is important.  Identify & Avoid failures -Identify failing bits using memory  ...  reduce by 50% -Good for L1 due to low latency  Bit-Fix penalties at low voltage -Latency +3 cycles -Capacity/Associativity reduce by 25% -Good for L2 due to minimal capacity loss Parameters at  ...  Configurable approach that "trades off cache capacity" -Maximizes performance at high voltage -Enables ~50% improvement in energy per instruction when operating at low voltage  ... 
doi:10.1145/1394608.1382139 fatcat:korwhq6b5fazbhvyadj2bef2hm

Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad Khellah, Shih-Lien Lu
2008 2008 International Symposium on Computer Architecture  
T Tr ra ad di in ng g o of ff f C Ca ac ch he e C Ca ap pa ac ci it ty y f fo or r R Re el li ia ab bi il li it ty y t to o E En na ab bl le e L Lo ow w V Vo ol lt ta ag ge e O Op pe er ra at ti io on  ...  Overview of c c c cache ache ache ache w w w word ord ord ord----d d d disable isable isable isable o o o operation peration peration peration im mi in na at te es s a a s si in ng gl le e d de ef fe  ...  operation of the bit level operation of the bit level operation of the bit level operation of the bit----fix fix fix fix scheme scheme scheme scheme O Op pe er ra at ti io on n i in n l lo ow w--v vo ol  ... 
doi:10.1109/isca.2008.22 dblp:conf/isca/WilkersonGACKL08 fatcat:4ppdnozlvzhphf57p6k5onxjwm

Improving cache lifetime reliability at ultra-low voltages

Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu
2009 Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture - Micro-42  
Like previous work on mitigating persistent failures, MS-ECC trades off cache capacity for lower voltages.  ...  In this paper, we propose a novel adaptive technique to improve cache lifetime reliability and enable low voltage operation.  ...  In this technique, we trade off cache capacity for reliability at low voltage.  ... 
doi:10.1145/1669112.1669126 dblp:conf/micro/ChishtiAWWL09 fatcat:4st6wodkbvhd5kijye4nu2pf3y

256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V

Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011 2011 18th IEEE International Conference on Electronics, Circuits, and Systems  
The proposed cache can dynamically enhance its reliability in the dependable mode, thereby trading off its performance.  ...  Our chip measurement results show that the proposed dependable cache possesses the scalable characteristic of reliability. Moreover, it can decrease the minimum operating voltage by 115 mV.  ...  Our proposed cache can trade off its associativity (the number of cache ways) with low-voltage reliability.  ... 
doi:10.1109/icecs.2011.6122328 dblp:conf/icecsys/JungNOKY11 fatcat:nfww73a4pfbqpg3znnz7ebxr5e

Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages

Alexandra Ferreron, Dario Suarez-Gracia, Jesus Alastruey-Benede, Teresa Monreal, Victor Vinals
2014 2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing  
A microarchitectural technique to cope with cache reliability at ultra-low voltages is block disabling; however, in many cases, the savings in on-chip caches do not compensate for the consumption in the  ...  However, the potential savings of voltage scaling are limited by the correct operation of SRAM cells, which is not guaranteed below Vdd min , the minimum voltage in which cache structures operate reliably  ...  EXPLOITING COHERENCE TO ENABLE EFFICIENT ULTRA-LOW VOLTAGE OPERATION Here, our explicit goal is to leverage a conventional two-level cache-inclusive CMP organization and assess low complexity modifications  ... 
doi:10.1109/sbac-pad.2014.12 dblp:conf/sbac-pad/Ferreron-LabariGAAV14 fatcat:cpzzpah3xfae5c7kzkwho3r2ju

Improving multi-core performance using mixed-cell cache architecture

S. M. Khan, A. R. Alameldeen, C. Wilkerson, J. Kulkarni, D. A. Jimenez
2013 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)  
Mixed-cell cache architectures, where part of the cache is designed with larger, more robust cells, enable caches to operate reliably at low voltage while minimizing the added cost of larger cells.  ...  But mixed-cell caches suffer from poor low-voltage scalability since caches can only use robust cells at low voltage, sacrificing up to 75% of cache capacity.  ...  Acknowledgements We are very grateful to Aamer Jaleel who helped us with his simulator, CMP$im. We thank the anonymous reviewers for their helpful feedback.  ... 
doi:10.1109/hpca.2013.6522312 dblp:conf/hpca/KhanAWKJ13 fatcat:4yibsdwmabe2rjzcdfoykhr5nm

Application-specific memory protection policies for energy-efficient reliable design

Sheng Yang, Rishad A. Shafik, Saqib Khursheed, David Flynn, Geoff V. Merrett, Bashir M. Al-hashimi
2015 2015 International Symposium on Rapid System Prototyping (RSP)  
We show that the joint consideration of cache resizing and VFS can improve the L1-Cache reliability by up to 5x compared to VFS alone, while incurring <10% energy overhead.  ...  Fundamental to such joint optimization is a design analysis framework, which can analyze trade-off between memory protection policies considering the impact of VFS, and apply design optimization algorithm  ...  This is achieved by enabling the processor to operate on more energy-efficient supply voltage, while still meeting the reliability constraints.  ... 
doi:10.1109/rsp.2015.7416541 dblp:conf/rsp/YangSKFMA15 fatcat:wxndh7x2pbeajn5e6qzotmnl3y

Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM

Jinwook JUNG, Yohei NAKATA, Shunsuke OKUMURA, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO
2013 IEICE transactions on electronics  
This paper presents an adaptive cache architecture for wide-range reliable low-voltage operations.  ...  We can obtain reliable low-voltage operations by application of the dependable mode to weaker pairs that cannot operate reliably at low voltages.  ...  Although the proposed cache downsizes its capacity and associativity for reliable low voltage operations, it cache can reconfigure its capacity and associativity when higher performance and large cache  ... 
doi:10.1587/transele.e96.c.528 fatcat:7qxpmohg2fhztoipjo3jihnuui

NVP: Non-uniform voltage and pulse width settings for power efficient hybrid STT-RAM

Reyhaneh Jabbarvand Behrouz, Houman Homayoun
2014 International Green Computing Conference  
Operating at low voltage increases the probability of failure.  ...  To address this problem, we propose a hybrid non-uniform cache architecture (NUCA) by combining SRAMs and STT-RAMs with different operating voltage/pulse width settings.  ...  It also demonstrates how this affects the power dissipation of large last level cache. • Proposes the concept of multiple low energy writes that enables low power and reliable LLC with non-uniform cache  ... 
doi:10.1109/igcc.2014.7039156 dblp:conf/green/BehrouzH14 fatcat:xdgewdfazjb47ayif46st7de5q

Multi-Layer Memory Resiliency

Nikil Dutt, Puneet Gupta, Alex Nicolau, Abbas BanaiyanMofrad, Mark Gottscho, Majid Shoushtari
2014 Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14  
With memories continuing to dominate the area, power, cost and performance of a design, there is a critical need to provision reliable, high-performance memory bandwidth for emerging applications.  ...  Two specific exemplars are used to illustrate multilayer memory resilience: first we describe static and dynamic policies to achieve energy savings in caches using aggressive voltage scaling combined with  ...  Many works in resilient SRAM caches target power reduction by enabling low voltage operation.  ... 
doi:10.1145/2593069.2596684 dblp:conf/dac/DuttGNBGS14 fatcat:v6rb7n5m5bfj5gbbgloksy7ckq

Performance-effective operation below Vcc-min

Nikolas Ladas, Yiannakis Sazeides, Veerle Desmet
2010 2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS)  
The goal of this paper is to minimize the performance loss due to reduced cache capacity when operating below Vcc-min. A simple method is proposed: disable faulty blocks at low voltage.  ...  For one configuration used in this paper, block disabling is shown to have on the average 6.6% and up to 29% better performance than a previously proposed scheme for low voltage cache operation.  ...  The authors would like to recognize Constantinos Kourouyiannis for helping with the preliminary studies leading to this work.  ... 
doi:10.1109/ispass.2010.5452017 dblp:conf/ispass/LadasSD10 fatcat:2tdaehxnvvdflmh2zot3enldme

Reconfigurable energy efficient near threshold cache architectures

Ronald G. Dreslinski, Gregory K. Chen, Trevor Mudge, David Blaauw, Dennis Sylvester, Krisztian Flautner
2008 2008 41st IEEE/ACM International Symposium on Microarchitecture  
We propose an embedded processor based on these new cache architectures that operates in a low power mode, with minimal impact on full performance runtime.  ...  Current commercial memory technologies have been limited in the degree of supply voltage scaling that can be performed if they are to meet yield and reliability constraints.  ...  Memory cells on the other hand require substantial resizing in order to maintain reliable operation at low voltages [25] . Chen et al.  ... 
doi:10.1109/micro.2008.4771813 dblp:conf/micro/DreslinskiCMBSF08 fatcat:6hyraltwlnhflnns3lzeku7whq

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Alexandra Ferreron, Dario Suarez-Gracia, Jesus Alastruey-Benede, Teresa Monreal-Arnal, Pablo Ibanez
2016 IEEE transactions on computers  
In this paper, we propose Concertina, an LLC designed to enable reliable operation at low voltages with conventional SRAM cells.  ...  , enabling use of 100% of the LLC capacity.  ...  ACKNOWLEDGMENTS The authors would like to thank Javier Olivito for his support with logic prototyping, Víctor Viñals for his insightful contributions to this paper, and the anonymous referees for their  ... 
doi:10.1109/tc.2015.2479585 fatcat:ndyxtieje5bavkewwibypqrk2e

Modeling and design exploration of FBDRAM as on-chip memory

Guangyu Sun, Cong Xu, Yuan Xie
2012 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
In order to mitigate the impact of process variations, we apply different error correction mechanisms and corresponding architecture-level modifications to FBDRAM caches and study the trade-off among reliability  ...  With this model, we explore the L2 cache design using FBDRAM and compare it with traditional SRAM/eDRAM caches in both circuit and architectural levels 1 .  ...  ACKNOWLEDGMENT The authors would like to thank Dr. Zhichao Lu and Dr. Jin Ouyang for making available some data and simulations.  ... 
doi:10.1109/date.2012.6176712 dblp:conf/date/SunXX12 fatcat:vajx3323tnh3vlpf5fxqa5i2zm

Macho: A failure model-oriented adaptive cache architecture to enable near-threshold voltage scaling

T. Mahmood, Soontae Kim, Seokin Hong
2013 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)  
Macho enables voltage scaling down to 400mV by tolerating high SRAM-failure rates (≥ 1%) and achieves better energy reduction (44%) than other substitution caches with similar area overheads.  ...  Recent interest in CMOS voltage scaling has produced a class of cache architectures which tolerate parametric SRAM failures at low voltage by substituting faulty words of one cache line with healthy words  ...  While resilient circuits and ECC try to recover whole cache at low voltages, variation-aware caches are proposed to gracefully degrade and trade-off cache capacity in the presence of persistent failures  ... 
doi:10.1109/hpca.2013.6522347 dblp:conf/hpca/MahmoodKH13 fatcat:sxlw6zlsincftilzh6snso3xoy
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