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Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad Khellah, Shih-Lien Lu
2008 SIGARCH Computer Architecture News  
As big as possible when performance is important (high voltages).  Trades off cache capacity to allow low voltage when power is important.  Identify & Avoid failures -Identify failing bits using memory  ...  .  Read is converse of write Bit-Fix  Use whole cache at high Vcc  ¼ of cache lines store repair info for other lines when operating at low voltage.  ...  Configurable approach that "trades off cache capacity" -Maximizes performance at high voltage -Enables ~50% improvement in energy per instruction when operating at low voltage  ... 
doi:10.1145/1394608.1382139 fatcat:korwhq6b5fazbhvyadj2bef2hm

Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad Khellah, Shih-Lien Lu
2008 2008 International Symposium on Computer Architecture  
Overview of c c c cache ache ache ache w w w word ord ord ord----d d d disable isable isable isable o o o operation peration peration peration im mi in na at te es s a a s si in ng gl le e d de ef fe  ...  operation of the bit level operation of the bit level operation of the bit level operation of the bit----fix fix fix fix scheme scheme scheme scheme O Op pe er ra at ti io on n i in n l lo ow w--v vo ol  ... 
doi:10.1109/isca.2008.22 dblp:conf/isca/WilkersonGACKL08 fatcat:4ppdnozlvzhphf57p6k5onxjwm

Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages

Alexandra Ferreron, Dario Suarez-Gracia, Jesus Alastruey-Benede, Teresa Monreal, Victor Vinals
2014 2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing  
A microarchitectural technique to cope with cache reliability at ultra-low voltages is block disabling; however, in many cases, the savings in on-chip caches do not compensate for the consumption in the  ...  However, the potential savings of voltage scaling are limited by the correct operation of SRAM cells, which is not guaranteed below Vdd min , the minimum voltage in which cache structures operate reliably  ...  I CAPACITY AVAILABLE AT LOW-VOLTAGES FOR 16-WAY, 1MB CACHE BANK WITH BLOCK DISABLING (BLOCK SIZE IS 64 BYTES).  ... 
doi:10.1109/sbac-pad.2014.12 dblp:conf/sbac-pad/Ferreron-LabariGAAV14 fatcat:cpzzpah3xfae5c7kzkwho3r2ju

Improving multi-core performance using mixed-cell cache architecture

S. M. Khan, A. R. Alameldeen, C. Wilkerson, J. Kulkarni, D. A. Jimenez
2013 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)  
But mixed-cell caches suffer from poor low-voltage scalability since caches can only use robust cells at low voltage, sacrificing up to 75% of cache capacity.  ...  Mixed-cell cache architectures, where part of the cache is designed with larger, more robust cells, enable caches to operate reliably at low voltage while minimizing the added cost of larger cells.  ...  We thank the anonymous reviewers for their helpful feedback.  ... 
doi:10.1109/hpca.2013.6522312 dblp:conf/hpca/KhanAWKJ13 fatcat:4yibsdwmabe2rjzcdfoykhr5nm

DPCS

Mark Gottscho, Abbas BanaiyanMofrad, Nikil Dutt, Alex Nicolau, Puneet Gupta
2015 ACM Transactions on Architecture and Code Optimization (TACO)  
Complex FTVS schemes are commonly proposed to achieve very low minimum supply voltages, but these can suffer from high overheads and thus do not always offer the best power/capacity trade-offs.  ...  Based on this observation, we propose a simple and low-overhead FTVS cache architecture for power/capacity scaling.  ...  Ghasemi et al. [2011] proposed a lastlevel cache with heterogeneous cell sizes for more graceful voltage/capacity trade-offs.  ... 
doi:10.1145/2792982 fatcat:wswxryw3nzehtahpdd5vlmuj2e

Improving cache lifetime reliability at ultra-low voltages

Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu
2009 Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture - Micro-42  
Like previous work on mitigating persistent failures, MS-ECC trades off cache capacity for lower voltages.  ...  In this paper, we propose a novel adaptive technique to improve cache lifetime reliability and enable low voltage operation.  ...  In this technique, we trade off cache capacity for reliability at low voltage.  ... 
doi:10.1145/1669112.1669126 dblp:conf/micro/ChishtiAWWL09 fatcat:4st6wodkbvhd5kijye4nu2pf3y

256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V

Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011 2011 18th IEEE International Conference on Electronics, Circuits, and Systems  
The proposed cache can dynamically enhance its reliability in the dependable mode, thereby trading off its performance.  ...  Our chip measurement results show that the proposed dependable cache possesses the scalable characteristic of reliability. Moreover, it can decrease the minimum operating voltage by 115 mV.  ...  Our proposed cache can trade off its associativity (the number of cache ways) with low-voltage reliability.  ... 
doi:10.1109/icecs.2011.6122328 dblp:conf/icecsys/JungNOKY11 fatcat:nfww73a4pfbqpg3znnz7ebxr5e

Modeling and design exploration of FBDRAM as on-chip memory

Guangyu Sun, Cong Xu, Yuan Xie
2012 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
In order to mitigate the impact of process variations, we apply different error correction mechanisms and corresponding architecture-level modifications to FBDRAM caches and study the trade-off among reliability  ...  With this model, we explore the L2 cache design using FBDRAM and compare it with traditional SRAM/eDRAM caches in both circuit and architectural levels 1 .  ...  Jin Ouyang for making available some data and simulations.  ... 
doi:10.1109/date.2012.6176712 dblp:conf/date/SunXX12 fatcat:vajx3323tnh3vlpf5fxqa5i2zm

Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM

Jinwook JUNG, Yohei NAKATA, Shunsuke OKUMURA, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO
2013 IEICE transactions on electronics  
Our chip measurement results show that the proposed cache can trade off its associativity with the minimum operating voltage.  ...  This paper presents an adaptive cache architecture for wide-range reliable low-voltage operations.  ...  Although the proposed cache downsizes its capacity and associativity for reliable low voltage operations, it cache can reconfigure its capacity and associativity when higher performance and large cache  ... 
doi:10.1587/transele.e96.c.528 fatcat:7qxpmohg2fhztoipjo3jihnuui

NVP: Non-uniform voltage and pulse width settings for power efficient hybrid STT-RAM

Reyhaneh Jabbarvand Behrouz, Houman Homayoun
2014 International Green Computing Conference  
Operating at low voltage increases the probability of failure.  ...  To address this problem, we propose a hybrid non-uniform cache architecture (NUCA) by combining SRAMs and STT-RAMs with different operating voltage/pulse width settings.  ...  further while operating at low voltage.  ... 
doi:10.1109/igcc.2014.7039156 dblp:conf/green/BehrouzH14 fatcat:xdgewdfazjb47ayif46st7de5q

System level power-performance trade-offs in embedded systems using voltage and frequency scaling of off-chip buses and memory

Kiran Puttaswamy, Kyu-Won Choi, Jun Cheol Park, Vincent J. Mooney, Abhijit Chatterjee, Peeter Ellervee
2002 Proceedings of the 15th international symposium on System Synthesis - ISSS '02  
This paper quantitatively explores voltage/frequency scaling of off-chip buses and memory as a means of trading off performance for power/energy at the system level in embedded systems.  ...  In this paper, for the case of an embedded system with one processor chip and one memory chip, we propose frequency and voltage scaling of the off-chip buses and the memory chip and use a known micro-architectural  ...  Or he might opt for low performance and very low power when executing low priority applications like checking e-mail.  ... 
doi:10.1145/581199.581249 fatcat:gxtwcxod7bakth3jkb6ayra2gq

System level power-performance trade-offs in embedded systems using voltage and frequency scaling of off-chip buses and memory

Kiran Puttaswamy, Kyu-Won Choi, Jun Cheol Park, Vincent J. Mooney, Abhijit Chatterjee, Peeter Ellervee
2002 Proceedings of the 15th international symposium on System Synthesis - ISSS '02  
This paper quantitatively explores voltage/frequency scaling of off-chip buses and memory as a means of trading off performance for power/energy at the system level in embedded systems.  ...  In this paper, for the case of an embedded system with one processor chip and one memory chip, we propose frequency and voltage scaling of the off-chip buses and the memory chip and use a known micro-architectural  ...  Or he might opt for low performance and very low power when executing low priority applications like checking e-mail.  ... 
doi:10.1145/581244.581249 fatcat:6ssgstuevjdl3mtr5u6p45yule

Combining RAM Technologies for Hard-error Recovery in L1 Data Caches Working at Very-low Power Modes

Vicente Lorente, Alejandro Valero, Julio Sahuquillo, Salvador Petit, Ramon Canal, Pedro Lopez, Jose Duato
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013  
Recent proposals provide a rather low fault-coverage due to the fault coverage/overhead trade-off.  ...  Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. IEEE, ACM.  ...  MOTIVATION The main reason of the low fault-coverage supported by existing proposals is that the devised solutions must trade off coverage for overhead (area, energy, performance, etc.).  ... 
doi:10.7873/date.2013.031 dblp:conf/date/LorenteVSPCLD13 fatcat:ndl46pf4wbeyvlnlvjmwclyp2m

Review and classification of gain cell eDRAM implementations

Adam Teman, Pascal Meinerzhagen, Andreas Burg, Alexander Fish
2012 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel  
Several industrial and academic publications have presented GC memory implementations for various target applications, including high-performance processor caches, wireless communication memories, and  ...  With the increasing requirement of a high-density, high-performance, low-power alternative to traditional SRAM, Gain Cell (GC) embedded DRAMs have gained a renewed interest in recent years.  ...  This trade-off is quite apparent in the cache designs, as the larger capacity systems [3, 5, 11] prefer the 2T topology at the cost of additional hardware to retain performance.  ... 
doi:10.1109/eeei.2012.6377022 fatcat:wrf43obipzeklny4fpnmg5bvky

Application-specific memory protection policies for energy-efficient reliable design

Sheng Yang, Rishad A. Shafik, Saqib Khursheed, David Flynn, Geoff V. Merrett, Bashir M. Al-hashimi
2015 2015 International Symposium on Rapid System Prototyping (RSP)  
Fundamental to such joint optimization is a design analysis framework, which can analyze trade-off between memory protection policies considering the impact of VFS, and apply design optimization algorithm  ...  Additionally, using selective ECC for L2-Cache and DRAM, we show that energy consumption can be reduced by up to 40%.  ...  For example without cache resizing, if the DRC is 25,000 FIT the only available operating voltage is 1.2V.  ... 
doi:10.1109/rsp.2015.7416541 dblp:conf/rsp/YangSKFMA15 fatcat:wxndh7x2pbeajn5e6qzotmnl3y
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