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Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors

María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas
2005 ACM Transactions on Architecture and Code Optimization (TACO)  
In this paper, we introduce a novel taxonomy of approaches to buffer and manage multiversion speculative memory state in multiprocessors.  ...  Thread-Level Speculation (TLS) provides architectural support to aggressively run hard-to-analyze code in parallel.  ...  BUFFERING MEMORY STATE Basics of Thread-Level Speculation Thread-Level Speculation (TLS) extracts tasks from sequential codes and executes them in parallel hoping not to violate any sequential semantics  ... 
doi:10.1145/1089008.1089010 fatcat:ekiblury4nbrximsgoxonogxhq

Tradeoffs in buffering memory state for thread-level speculation in multiprocessors

M.J. Garzaran, M. Prvulovic, J.M. Llaberia, V. Vinals, L. Rauchwerger, J. Torrellas
The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.  
In this paper, we introduce a novel taxonomy of approaches to buffer and manage multi-version speculative memory state in multiprocessors.  ...  Thread-level speculation provides architectural support to aggressively run hard-to-analyze code in parallel.  ...  First, it introduces a novel taxonomy of approaches to buffer multi-version memory state for thread-level speculation in multiprocessors.  ... 
doi:10.1109/hpca.2003.1183537 dblp:conf/hpca/GarzaranPLVRT03 fatcat:7pfbgbkcl5g7zgrpfzlws3n264

Respec

Dongyoon Lee, Benjamin Wester, Kaushik Veeraraghavan, Satish Narayanasamy, Peter M. Chen, Jason Flinn
2010 SIGPLAN notices  
Our software system adds on average about 18% overhead to the execution time for recording and replaying programs with two threads and 55% overhead for programs with four threads.  ...  This paper presents Respec, a new way to support deterministic replay of shared memory multithreaded programs on commodity multiprocessor hardware.  ...  Acknowledgments We thank the anonymous reviewers for comments that improved this paper. The work is supported by the National Science Foundation under award CNS-0905149.  ... 
doi:10.1145/1735971.1736031 fatcat:fd2hikuo2rcavkgcusmqxnlc4u

Parallelism exploitation in superscalar multiprocessing

N.-P. Lu, C.-P. Chung
1998 IEE Proceedings - Computers and digital Techniques  
This simulator models both a superscalar processor that can exploit instruction-level parallelism, and a shared-memory multiprocessor system that can exploit task-level parallelism.  ...  Recently, the authors have developed a simulator for evaluating superscalar multiprocessor systems.  ...  While the register file contains the in-order state data, the reorder buffer contains the look-ahead state data.  ... 
doi:10.1049/ip-cdt:19981955 fatcat:ih24325o5jcijevm5hwntouove

Respec

Dongyoon Lee, Benjamin Wester, Kaushik Veeraraghavan, Satish Narayanasamy, Peter M. Chen, Jason Flinn
2010 SIGARCH Computer Architecture News  
Our software system adds on average about 18% overhead to the execution time for recording and replaying programs with two threads and 55% overhead for programs with four threads.  ...  This paper presents Respec, a new way to support deterministic replay of shared memory multithreaded programs on commodity multiprocessor hardware.  ...  Acknowledgments We thank the anonymous reviewers for comments that improved this paper. The work is supported by the National Science Foundation under award CNS-0905149.  ... 
doi:10.1145/1735970.1736031 fatcat:wfz7ipo4ibg7xlug5ggdgiupue

Respec

Dongyoon Lee, Benjamin Wester, Kaushik Veeraraghavan, Satish Narayanasamy, Peter M. Chen, Jason Flinn
2010 Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems - ASPLOS '10  
Our software system adds on average about 18% overhead to the execution time for recording and replaying programs with two threads and 55% overhead for programs with four threads.  ...  This paper presents Respec, a new way to support deterministic replay of shared memory multithreaded programs on commodity multiprocessor hardware.  ...  Acknowledgments We thank the anonymous reviewers for comments that improved this paper. The work is supported by the National Science Foundation under award CNS-0905149.  ... 
doi:10.1145/1736020.1736031 dblp:conf/asplos/LeeWVNCF10 fatcat:hihjdaere5h75l5gywh2hlk5n4

A survey of processors with explicit multithreading

Theo Ungerer, Borut Robič, Jurij Šilc
2003 ACM Computing Surveys  
The contexts of two or more threads of control are often stored in separate on-chip register sets.  ...  Explicit multithreaded processors are multithreaded processors that apply processes or operating system threads in their hardware thread slots.  ...  ACKNOWLEDGMENTS The authors would like to thank anonymous reviewers for many valuable comments.  ... 
doi:10.1145/641865.641867 fatcat:u6x7jdmkfvexnm3culskjsoxwi

Recent advances in memory consistency models for hardware shared memory systems

S.V. Adve, V.S. Pai, P. Ranganathan
1999 Proceedings of the IEEE  
The memory consistency model for a system typically involves a tradeoff between performance and programmability.  ...  The memory consistency model of a shared memory system determines the order in which memory operations will appear to execute to the programmer.  ...  Pugh for correcting the description of the Java memory model in an earlier version of this paper. They would also like to thank V. Adve and K.  ... 
doi:10.1109/5.747865 fatcat:mqmur5e7pzczxbvb76mcgju3oy

Reducing misspeculation overhead for module-level speculative execution

Fredrik Warg, Per Stenstrom
2005 Proceedings of the 2nd conference on Computing frontiers - CF '05  
Thread-level speculative execution is a technique that makes it possible for a wider range of single-threaded applications to make use of the processing resources in a chip multiprocessor.  ...  We show that the overhead when spawning speculative threads for all module continuations is on average three times as big as the time spent on useful execution on our baseline 8-way chip multiprocessor  ...  Buffer space for speculative state is unlimited. head. However, since the baseline system will incur more misspeculations, the overhead associated with the memory system will be higher.  ... 
doi:10.1145/1062261.1062310 dblp:conf/cf/WargS05 fatcat:ejlcgrszofhqblyvhxipe4iiji

Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency

Kunle Olukotun, Lance Hammond, James Laudon
2007 Synthesis Lectures on Computer Architecture  
Buffers may fill up during long running threads that write too much state out to memory.  ...  Since threads may only complete in order, the buffers therefore act as a sort of reorder buffer for memory references.  ...  Also, the large loop body may overflow the buffers holding the speculative state.  ... 
doi:10.2200/s00093ed1v01y200707cac003 fatcat:qyjilavdhfcmlnc46l5sxg7ssq

Hybrid transactional memory

Sanjeev Kumar, Michael Chu, Christopher J. Hughes, Partha Kundu, Anthony Nguyen
2006 Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '06  
Transactional memory can be implemented in either hardware or software.  ...  When a transaction commits, all operations within the transaction become visible to other threads. When it aborts, all operations in the transaction are rolled back.  ...  We would like to thank our shepherd, Tim Harris, for his detailed and thoughtful comments.  ... 
doi:10.1145/1122971.1123003 dblp:conf/ppopp/KumarCHKN06 fatcat:h4cxd2z63jbdxmjbsp5cuexgqe

Energy reduction in multiprocessor systems using transactional memory

Tali Moreshet, R.I. Bahar, M. Herlihy
2005 ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.  
In this work we focus on new energy consumption issues unique to multiprocessor systems: synchronization of accesses to shared memory.  ...  We show that transactional memory has an advantage in terms of energy consumption over locks, but that this advantage largely depends on the system architecture, the contention level, and the policy of  ...  Acknowledgments We thank Fen Xie for help with Simics, and Tom Doeppner for helpful advice on OS issues.  ... 
doi:10.1109/lpe.2005.195542 fatcat:ohnr3nfnijgabgivvyeipmgcfu

Energy reduction in multiprocessor systems using transactional memory

Tali Moreshet, R. Iris Bahar, Maurice Herlihy
2005 Proceedings of the 2005 international symposium on Low power electronics and design - ISLPED '05  
In this work we focus on new energy consumption issues unique to multiprocessor systems: synchronization of accesses to shared memory.  ...  We show that transactional memory has an advantage in terms of energy consumption over locks, but that this advantage largely depends on the system architecture, the contention level, and the policy of  ...  Acknowledgments We thank Fen Xie for help with Simics, and Tom Doeppner for helpful advice on OS issues.  ... 
doi:10.1145/1077603.1077683 dblp:conf/islped/MoreshetBH05 fatcat:n2yqcqewbrfxfjoiujxooa6ocy

A Resolution for Shared Memory Conflict in Multiprocessor System-on-a-Chip [article]

Shaily Mittal, Nitin
2012 arXiv   pre-print
In this paper, we propose a new semaphore scheme for synchronization in shared cache memory in an MPSoC.  ...  Now days, manufacturers are focusing on increasing the concurrency in multiprocessor system-on-a-chip (MPSoC) architecture instead of increasing clock speed, for embedded systems.  ...  in shared-memory multiprocessors.  ... 
arXiv:1202.0613v1 fatcat:27ky77b3nrgj3g6eupgkitblwq

The shared-thread multiprocessor

Jeffery A. Brown, Dean M. Tullsen
2008 Proceedings of the 22nd annual international conference on Supercomputing - ICS '08  
This paper describes initial results for an architecture called the Shared-Thread Multiprocessor (STMP).  ...  This shared thread state allows the system to schedule threads from a shared pool onto individual cores, allowing for rapid movement of threads between cores.  ...  Acknowledgments The authors would like to thank the anonymous reviewers for their helpful insights.  ... 
doi:10.1145/1375527.1375541 dblp:conf/ics/BrownT08 fatcat:whmgnelnu5hczkhhls4q2eqgte
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