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Traces as a Solution to Pessimism and Modeling Costs in WCET Analysis

Jack Whitham, Neil Audsley, Marc Herbstritt
2008
In this paper the benefits and costs of traces are discussed. Advantages of traces include a reduction in pessimism in WCET analysis, with the need to accurately model CPU internals removed.  ...  WCET analysis models for superscalar out-of-order CPUs generally need to be pessimistic in order to account for a wide range of possible dynamic behavior.  ...  As a timing model, a trace is a subgraph of a timing graph (T-graph), as proposed in [18] for WCET analysis using IPET. The model is: 1.  ... 
doi:10.4230/oasics.wcet.2008.1666 fatcat:7wpwbgqrkjdd3km5wpsnxtw7py

Context-Sensitive Measurement-Based Worst-Case Execution Time Estimation

Michael Zolda, Sven Bunte, Raimund Kirner
2011 2011 IEEE 17th International Conference on Embedded and Real-Time Computing Systems and Applications  
on the target hardware and analyzing the obtained time-stamped execution traces.  ...  The goal of measurement-based WCET estimation (MBWE) is to derive an estimate of the worst-case execution time (WCET) of a given piece of software on a particular target platform by executing the software  ...  ACKNOWLEDGMENT The research leading to these results has received funding from IST FP-7 project "Asynchronous and Dynamic Virtualization through performance ANalysis to support Concurrency Engineering  ... 
doi:10.1109/rtcsa.2011.73 dblp:conf/rtcsa/ZoldaBK11 fatcat:d2qzlebukfa6lhed2xngdd6efu

Worst-Case Energy-Consumption Analysis by Microarchitecture-Aware Timing Analysis for Device-Driven Cyber-Physical Systems

Phillip Raffeck, Christian Eichler, Peter Wägemann, Wolfgang Schröder-Preikschat, Michael Wagner
2019 Worst-Case Execution Time Analysis  
reduces analysis pessimism in whole-system WCEC analyses.  ...  Unfortunately, WCET analysis approaches are not directly applicable for deriving WCEC bounds in device-driven cyber-physical systems: For example, a single memory operation can lead to a significant power-consumption  ...  This information is used as costs in a WCRE formulation. Our evaluations show that this composite analysis significantly reduces analysis pessimism.  ... 
doi:10.4230/oasics.wcet.2019.4 dblp:conf/wcet/RaffeckEWS19 fatcat:vnk7phhis5dx7nmh36wqhkeufa

Contention in Multicore Hardware Shared Resources: Understanding of the State of the Art

Gabriel Fernandez, Jaume Abella, Eduardo Quiñones, Christine Rochange, Tullio Vardanega, Francisco J. Cazorla, Marc Herbstritt
2014 Worst-Case Execution Time Analysis  
This sparseness makes it difficult for any reader to form a coherent picture of the problem and solution space.  ...  This paper draws a tentative taxonomy in which each known approach to the problem can be categorised based on its specific goals and assumptions.  ...  The research leading to this work has received funding from: COST Action IC1202, Timing Analysis On Code-Level (TACLe); and the parMERASA and PROX-IMA grant agreements (respectively no. 287519 and 611085  ... 
doi:10.4230/oasics.wcet.2014.31 dblp:conf/wcet/FernandezAQRVC14 fatcat:xfhpnrtmf5a65ek3upravfesca

Hybrid measurement-based WCET analysis at the source level using object-level traces

Adam Betts, Nicholas Merriam, Guillem Bernat, Marc Herbstritt
2010 Worst-Case Execution Time Analysis  
Meaningful WCET analysis involves not just running a tool to obtain an overall WCET value but also understanding which sections of code consume most of the WCET in order that corrective actions, such as  ...  In order to make the necessary measurements, instrumentation code is added to generate a timestamped trace from the running program.  ...  Figure 1 C 1 Macro to Generate Assembly Label Ipoint able to parse a trace in (address, timestamp) format and therefore perform the WCET analysis.  ... 
doi:10.4230/oasics.wcet.2010.54 dblp:conf/wcet/BettsMB10 fatcat:kunliacf4bbyjitm56dhgz5se4

Reconciling Time Predictability and Performance in Future Computing Systems

Francisco J. Cazorla, Jaume Abella, Enrico Mezzetti, Carles Hernandez, Tullio Vardanega, Guillem Bernat
2018 IEEE design & test  
This paper presents low-overhead solutions for hardware design and timing analysis to help attain the desired level of predictable performance in all application domains with assurance needs, also contributing  ...  Satisfying this need in a cost-effective manner compels system architects to use high-performance hardware units, which however have disruptive effects on current timing verification practice.  ...  STA will continue to be the reference timing analysis solution for more restricted scenarios and lower-performance systems in which accurate abstract modelling is still possible.  ... 
doi:10.1109/mdat.2017.2766558 fatcat:bmga2zhfzfapxelfclfe7pjgny

A generic and compositional framework for multicore response time analysis

Sebastian Altmeyer, Robert I. Davis, Leandro Indrusiak, Claire Maiza, Vincent Nelis, Jan Reineke
2015 Proceedings of the 23rd International Conference on Real Time and Networks Systems - RTNS '15  
In this paper, we introduce a Multicore Response Time Analysis (MRTA) framework.  ...  The MRTA framework decouples response time analysis from a reliance on context independent WCET values.  ...  Acknowledgements This work was supported in part by the COST Action IC1202 TACLe, by the DFG as part of the Transregional Collaborative Research Centre SFB/TR 14 (AVACS), by National Funds through FCT/  ... 
doi:10.1145/2834848.2834862 dblp:conf/rtns/AltmeyerDIMNR15 fatcat:4ad3vtbawjer7otj44q4dbotqe

Calculating WCET estimates from timed traces

Michael Zolda, Raimund Kirner
2015 Real-time systems  
Static analysis tools that could yield sufficiently tight WCET bounds are often unavailable. As a result, interest in portable analysis approaches like measurement-based timing analysis is growing.  ...  However, determining exact WCETs is practically infeasible in cost-constrained industrial settings involving real-life code and COTS hardware.  ...  Systems" (FORTAS-RT) under contract P19230-N13, by the EU FP-7 project "Asynchronous and Dynamic  ... 
doi:10.1007/s11241-015-9240-1 fatcat:h6rsbmujszfnpjjqg6a3is33ha

Guaranteed Loop Bound Identification from Program Traces for WCET

Mark Bartlett, Iain Bate, Dimitar Kazakov
2009 2009 15th IEEE Real-Time and Embedded Technology and Applications Symposium  
It is proven that values are guaranteed to be correct using information obtainable from a finite and quantifiable number of program traces.  ...  Static analysis can be used to determine safe estimates of Worst Case Execution Time.  ...  However, this will also inevitably introduce pessimism in the general case, as WCET estimation is undecidable [8] .  ... 
doi:10.1109/rtas.2009.29 dblp:conf/rtas/BartlettBK09 fatcat:lblsouzt45e5bbyozbj7iiuhvm

Time-Predictable Embedded Software on Multi-Core Platforms: Analysis and Optimization

Sudipta Chattopadhyay, Abhik Roychoudhury, Jakob Rosén, Petru Eles, Zebo Peng
2014 Foundations and Trends® in Electronic Design Automation  
Specifically, part of the discussion in section 3 has been published in [21] , [22] and [18] . Besides, some content of section 4 has been published previously in [69] , [9] and [70] .  ...  Acknowledgements Part of the material discussed in this monograph has previously been published in different proceedings and journals.  ...  Therefore, we believe that hardware and software level solutions are required to reduce such pessimism for applying WCET analysis in practice.  ... 
doi:10.1561/1000000037 fatcat:r6mishcfabevvjuoq5k7rdzsfu

A Survey of WCET Analysis of Real-Time Operating Systems

Mingsong Lv, Nan Guan, Yi Zhang, Qingxu Deng, Ge Yu, Jianming Zhang
2009 2009 International Conference on Embedded Software and Systems  
Timing analysis of realtime systems considering both applications and RTOS has not been fully studied. So we intend to give a survey of related work on WCET analysis of RTOS.  ...  Traditional WCET analysis mainly deals with application programs and has achieved success in industry.  ...  The author defined the biggest obstacle to composable WCET analysis as "side effects": task interactions that cannot be traced back to the interfaces between tasks and their environment.  ... 
doi:10.1109/icess.2009.24 dblp:conf/icess/LvGZDYZ09 fatcat:gtueqpoqy5ew5ptjkunsbx75t4

Heterogeneous MPSoCs for Mixed Criticality Systems: Challenges and Opportunities [article]

Mohamed Hassan
2017 arXiv   pre-print
Due to their cost, performance, area, and energy efficiency, MPSoCs offer appealing architecture for emerging mixed criticality systems (MCS) such as driverless cars, smart power grids, and healthcare  ...  We outline existing solutions, highlight the necessary considerations for MPSoCs including both opportunities they create and research directions yet to be explored.  ...  This observation resulted in representing the WCET as a function in the criticality level, C(l). The majority of MCS papers consider a model of only two CLs, LO and HI [9] .  ... 
arXiv:1706.07429v1 fatcat:5jqdhovqpba5vbagwsrxc6e2fa

Methodologies for the WCET Analysis of Parallel Applications on Many-Core Architectures

Vincent Nelis, Patrick Meumeu Yomsi, Luis Miguel Pinho
2015 2015 Euromicro Conference on Digital System Design  
In this context, the paper discusses the application of the currently-available WCET analysis techniques and tools on such platforms and with highly parallel activities.  ...  In this context, the paper discusses the application of the currently-available WCET analysis techniques and tools on such platforms and with highly parallel activities.  ...  ACKNOWLEDGEMENTS This work was partially supported by National Funds through FCT/MEC (Portuguese Foundation for Science and Technology) and when applicable, co-financed by ERDF (  ... 
doi:10.1109/dsd.2015.105 dblp:conf/dsd/NelisYP15 fatcat:e3swrmvesnewzeranon3e7c7uy

DVFS and Its Architectural Simulation Models for Improving Energy Efficiency of Complex Embedded Systems in Early Design Phase

Haririan
2020 Computers  
Although RTL (Register-Transfer Level) models are more precise and reliable, system-level modeling enables the power and performance analysis of complex and dense designs in the early design phase.  ...  Power and performance are the main concerns beside others. Pre-silicon analysis of power and performance in today's complex embedded designs is a big challenge.  ...  WCET is usually a pessimistic estimation, and in this model, the WCET of a task with higher criticality is even more pessimistic, i.e., the pessimism in estimating the WCET depends on the criticality level  ... 
doi:10.3390/computers9010002 fatcat:4updttelvjadxlsk2xqmc2spt4

An extensible framework for multicore response time analysis

Robert I. Davis, Sebastian Altmeyer, Leandro S. Indrusiak, Claire Maiza, Vincent Nelis, Jan Reineke
2017 Real-time systems  
An extensible framework for multicore response time analysis Davis, R.I.; Altmeyer, S.J.; Indrusiak, L.S.; Maiza, C.; Nelis, V.; Reineke, J.  ...  as part of the project PEP, by National Funds through FCT/MEC (Portuguese Foundation for Science and Technology) and co-financed by ERDF (European Regional Development  ...  Acknowledgements This work was supported in part by the COST Action IC1202 TACLe, by the NWO Veni Project 'The time is now: Timing Verification for Safety-Critical Multi-Cores' by the Deutsche Forschungsgemeinschaft  ... 
doi:10.1007/s11241-017-9285-4 fatcat:dg6qbbdzfnajxlbsje57ku2ryi
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