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On-chip stimuli generation for post-silicon validation
2012
2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)
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This paper motivates the need for developing structured methods for porting the controllability aspects of pre-silicon verification into post-silicon validation environments. ...
In contrast to pre-silicon verification environments, insystem validation is not strongly constrained by the number of stimuli that can be applied; rather, the quality of the patterns, as well as the observation ...
Introduction A key step in the implementation flow of very large scale integrated (VLSI) circuits is pre-silicon verification. ...
doi:10.1109/hldvt.2012.6418251
dblp:conf/hldvt/Nicolici12
fatcat:3iwccztgjvbaniodgcb4wpbd6q
Robust System Design
2010
2010 23rd International Conference on VLSI Design
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For coming generations of silicon technologies, several causes of hardware failures, largely benign in the past, are becoming significant at the system-level. 3. ...
New approaches to thorough validation that can cope with tremendous growth in complexity. 2. Cost-effective tolerance and prediction of failures in hardware during system operation. 3. ...
Post-silicon validation is becoming significantly expensive. Intel reported headcount ratio of 3 : 1 for design vs. post-silicon validation 121) . ...
doi:10.1109/vlsi.design.2010.77
dblp:conf/vlsid/Mitra10
fatcat:5vkftdsnejg5fbylfuhtf62wzu
Robust System Design
2011
IPSJ Transactions on System LSI Design Methodology
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For coming generations of silicon technologies, several causes of hardware failures, largely benign in the past, are becoming significant at the system-level. 3. ...
New approaches to thorough validation that can cope with tremendous growth in complexity. 2. Cost-effective tolerance and prediction of failures in hardware during system operation. 3. ...
Post-silicon validation is becoming significantly expensive. Intel reported headcount ratio of 3 : 1 for design vs. post-silicon validation 121) . ...
doi:10.2197/ipsjtsldm.4.2
fatcat:jwoqglwa4fds7gzyhjnixvs7bq
Guest Editorial
2019
Journal of electronic testing
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To deal with this problem, the second paper proposes a signal tracing methodology for SAT-based error localization in the post-silicon environment. ...
Experimental results on a variety of benchmark circuits show that the proposed method succeeds in the post-silicon environment for two kinds of error scenarios. ...
doi:10.1007/s10836-019-05836-6
fatcat:lgtoq6c2wbg63jtfdpzv6eysba
Automated trace signals identification and state restoration for improving observability in post-silicon validation
2008
Proceedings of the conference on Design, automation and test in Europe - DATE '08
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Embedded logic analysis has emerged as a powerful technique for identifying functional bugs during postsilicon validation, as it enables at-speed acquisition of data from the circuit nodes in real-time ...
This paper introduces an automated method for improving the utilization of the on-chip storage, by identifying a small set of trace signals from which a large number of states can be restored using a compute-efficient ...
In order to facilitate real-time data acquisition during post-silicon validation, the trace buffer-based technique is employed. ...
doi:10.1145/1403375.1403689
fatcat:p4p4lcscyffkfejbd62vj6gioi
Observability-aware Directed Test Generation for Soft Errors and Crosstalk Faults
2013
2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems
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Post-silicon validation has emerged as an important component of any chip design methodology to detect both functional and electrical errors that have escaped the pre-silicon validation phase. ...
Our experimental results demonstrate that our approach can significantly improve error detection performance -on an average 58% for crosstalk faults and 48% for soft errors compared to existing techniques ...
Post-silicon validation is used to capture these bugs. An overview of post-silicon validation is shown in Figure 1 . A small set of signals are traced during execution. ...
doi:10.1109/vlsid.2013.203
dblp:conf/vlsid/BasuMP13
fatcat:rq7drc5ctnfsjaj3mreqoiliai
An Event-Based Neural Network Architecture With an Asynchronous Programmable Synaptic Memory
2014
IEEE Transactions on Biomedical Circuits and Systems
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Index Terms-Address event representation (AER), analog/digital, asynchronous, circuit, event-based, learning, neural network, neuromorphic, programmable weights, real-time, sensory-motor, silicon neuron ...
The fabricated chip comprises a total of 32 32 SRAM cells, 4 32 synapse circuits and 32 1 silicon neurons. ...
Whatley for constructive feedback on the manuscript, and the NCS group of the Institute of Neuroinformatics (http://ncs.ethz.ch/) for support and contributions to the development of the AER experimental ...
doi:10.1109/tbcas.2013.2255873
pmid:24681923
fatcat:gckgyknizfapjcshxnn3yva3xm
Automated Debugging from Pre-Silicon to Post-Silicon
[chapter]
2014
Debug Automation from Pre-Silicon to Post-Silicon
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The approach is based on model-based diagnosis. Diagnostic traces are proposed as an enhancement reducing debugging time and increasing diagnosis accuracy. ...
The experimental results show the effectiveness of the approach in post-silicon debugging. ...
Automated Flow for Post-Silicon Debugging
B. ...
doi:10.1007/978-3-319-09309-3_4
fatcat:5vn3vvmc6bbydaen4t6v66bxum
Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs
2013
Journal of electronic testing
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This has resulted in an increasing trend in design errors, manufacturing flaws, and security holes in modern VLSI systems. ...
With increasing sophistication of VLSI technology, process, and architecture, microprocessors and SoC systems continue to increase in complexity. ...
In particular, he leads projects on observability constraints and metrics for post-silicon debug quality, and techniques for post-silicon test readiness. ...
doi:10.1007/s10836-013-5411-y
fatcat:zfhwpkfkmfhivjtpsxsgu5wlry
Automated debugging from pre-silicon to post-silicon
2012
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
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The approach is based on model-based diagnosis. Diagnostic traces are proposed as an enhancement reducing debugging time and increasing diagnosis accuracy. ...
The experimental results show the effectiveness of the approach in post-silicon debugging. ...
Automated Flow for Post-Silicon Debugging
B. ...
doi:10.1109/ddecs.2012.6219082
dblp:conf/ddecs/DehbashiF12
fatcat:q4xqraylffdanhhqdfh3dgm2q4
Efficient Trace Signal Selection for Post Silicon Validation and Debug
2011
2011 24th Internatioal Conference on VLSI Design
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Post-silicon validation is an essential part of modern integrated circuit design to capture bugs and design errors that escape pre-silicon validation phase. ...
Storage requirements limit the number of signals that can be traced; therefore, a major challenge is how to reconstruct the majority of the remaining signals based on traced values. ...
Post-silicon validation techniques are used to capture these escaped bugs. Post-silicon debug comprises of signal observation and analysis. ...
doi:10.1109/vlsid.2011.14
dblp:conf/vlsid/BasuM11
fatcat:6ikf3djpw5gwrpnymiwbe5rizm
A New Post-Silicon Debug Approach Based on Suspect Window
2009
2009 27th IEEE VLSI Test Symposium
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Bugs are tending to be unavoidable in the design of complex integrated circuits. It is imperative to identify the bugs as soon as possible by post-silicon debug. ...
The main challenge for post-silicon debug is the observability of the internal signals. This paper exploits the fact that it is not necessary to observe the error free states. ...
Unlike previous work, we propose a suspect window based post-silicon debug mechanism, which combines the advantages of both scan-based and trace-based techniques. ...
doi:10.1109/vts.2009.35
dblp:conf/vts/GaoHL09
fatcat:xlmjqmiu4jbgbchalql6b6nsw4
Automated Post-Silicon Debugging of Failing Speedpaths
2012
2012 IEEE 21st Asian Test Symposium
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Debugging of speed-limiting paths (speedpaths) is a key challenge in development of Very-Large-Scale Integrated (VLSI) circuits as timing variations induced by process and environmental effects are increasing ...
First timing behavior of a circuit and corresponding variation models are converted into a functional domain. Then, our automated debugging based on Boolean Satisfiability (SAT) diagnoses speedpaths. ...
Post-silicon validation involves applying test vectors to the chip in order to verify its correct behavior. ...
doi:10.1109/ats.2012.42
dblp:conf/ats/DehbashiF12
fatcat:3yylfq272vfu7mg5wbhcirkjdm
Real-Time Classification of Complex Patterns Using Spike-Based Learning in Neuromorphic VLSI
2009
IEEE Transactions on Biomedical Circuits and Systems
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Here we demonstrate real-time classification of complex patterns of mean firing rates, using a VLSI network of spiking neurons and dynamic synapses which implement a robust spike-driven plasticity mechanism ...
We describe the implementation of this learning mechanism and present experimental data that demonstrate how the VLSI neural network can learn to classify patterns of neural activities, also in the case ...
Index Terms-Classification, learning, neuromorphic VLSI, silicon neuron, silicon synapse, spike-based plasticity, synaptic dynamics.
I. ...
doi:10.1109/tbcas.2008.2005781
pmid:23853161
fatcat:frs4bmxhf5fzxklqbnxrmkkzjm
Automated Selection of Signals to Observe for Efficient Silicon Debug
2009
2009 27th IEEE VLSI Test Symposium
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VLSI Test Symposium ...
Experimental results indicate that the cycle in which a bug first appears can be more rapidly and precisely found with the proposed approach thereby speeding up the post-silicon debug process. 27th IEEE ...
Acknowledgement The authors would like to thank Wooyoung Jang at the University of Texas at Austin for providing the NOC design used for the experiments. ...
doi:10.1109/vts.2009.51
dblp:conf/vts/YangT09
fatcat:cikh65j74bb73bf4iy6qd3szvq
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