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Trace signal selection for visibility enhancement in post-silicon validation

Xiao Liu, Qiang Xu
2009 2009 Design, Automation & Test in Europe Conference & Exhibition  
This paper proposes an automated trace signal selection strategy that is able to dramatically enhance the visibility in post-silicon validation.  ...  . • we define the gate-level restorabilities for visibility enhancement in a theoretically-precise manner;  ...  Acknowledgements This work was supported in part by the General Research  ... 
doi:10.1109/date.2009.5090872 dblp:conf/date/LiuX09 fatcat:hauzr6yh7bctfkz7ms5t2oiq5u

Intel's Post Silicon functional validation approach

Bojan Tommy, Frumkin Igor, Mauri Robert
2007 2007 IEEE International High Level Design Validation and Test Workshop  
Post silicon validation is the final process in semiconductor chip manufacturing. Functional Validation (FV) is one among many methods used in post silicon validation.  ...  In this paper we tried to explain how this post silicon functional validation is performed in the industry level.  ...  Threadmill: A post-silicon and Hishm Ashraf of STMicroelectronics for their exerciser for multi-threaded processors. InDesign immense contribution to this paper.  ... 
doi:10.1109/hldvt.2007.4392786 dblp:conf/hldvt/BojanFM07 fatcat:ygexaxoke5fwtl756u6jq4eulu

On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon Validation

Xiao Liu, Qiang Xu
2010 2010 19th IEEE Asian Test Symposium  
Since tracing all speedpath-related signals can cause prohibited design for debug (DfD) overhead, we present an automated trace signal selection methodology that maximizes error detection probability under  ...  One of the most challenging problems in post-silicon validation is to identify those errors that cause prohibitive extra delay on speedpaths in the circuit under debug (CUD) and only expose themselves  ...  To the best of our knowledge, this is the first trace-based solution for debugging electrical errors in general logic circuits in post-silicon validation.  ... 
doi:10.1109/ats.2010.50 dblp:conf/ats/LiuX10 fatcat:lj4kere6kzd6zctoxerwodaxfq

On signal tracing in post-silicon validation

Qiang Xu, Xiao Liu
2010 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)  
It is increasingly difficult to guarantee the first silicon success for complex integrated circuit (IC) designs. Post-silicon validation has thus become an essential step in the IC design flow.  ...  Tracing internal signals during circuit's normal operation, being able to provide real-time visibility to the circuit under debug (CUD), is one of the most effective silicon debug techniques and has gained  ...  CONCLUSION AND FUTURE WORK Trace-based debug techniques have been successfully applied in the industry for some time and they are shown to be quite effective for post-silicon validation.  ... 
doi:10.1109/aspdac.2010.5419883 dblp:conf/aspdac/XuL10 fatcat:5ftlnjsgmbf6ro5vvlufbfvnhq

Trace signal selection to enhance timing and logic visibility in post-silicon validation

Hamid Shojaei, Azadeh Davoodi
2010 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)  
Due to limitation in the bandwidth of trace buffers, only few state elements can be selected for tracing.  ...  In addition, we observe that different selections of trace signals can result in the same quality, measured as a logic visibility metric.  ...  These signals are selected for tracing at the design stage and the traces are analyzed at the post-silicon stage to debug logic errors.  ... 
doi:10.1109/iccad.2010.5654123 dblp:conf/iccad/ShojaeiD10 fatcat:tllr7dv5wfcztlfqqso2skmfta

Topological Ordering Signal Selection Technique for Internet of Things based on Combinational Gate for Visibility Enhancement

Agalya Rajendran, Muthaiah Rajappa
2020 Scalable Computing : Practice and Experience  
This shrinking market reduces the design automation validation process. Signal selection is the most effective and challenging technique in post-silicon validation and debug.  ...  This tends to select the signals prudently in order to maximize the state reconstruction. To identify the trace signals, signal restoration is the extensive metric that has been used so far.  ...  The authors sincerely thank DST-INSPIRE Fellowship and SASTRA Deemed University for providing a great support.  ... 
doi:10.12694/scpe.v21i1.1607 fatcat:gr5cgtbmyjdprnzifeup4qft2u

Post-silicon validation opportunities, challenges and recent advances

Subhasish Mitra, Sanjit A. Seshia, Nicola Nicolici
2010 Proceedings of the 47th Design Automation Conference on - DAC '10  
As a result, post-silicon validation is an emerging research topic with several exciting opportunities for major innovations in electronic design automation.  ...  Post-silicon validation is used to detect and fix bugs in integrated circuits and systems after manufacture.  ...  Acknowledgment This work is supported in part by the Semiconductor Research Corporation (SRC), the Gigascale Systems Research Center, one of six research centers funded under the Focus Center Research  ... 
doi:10.1145/1837274.1837280 dblp:conf/dac/MitraSN10 fatcat:hwycqj5eljfxbnszwn3zn5yjmy

On multiplexed signal tracing for post-silicon debug

Xiao Liu, Qiang Xu
2011 2011 Design, Automation & Test in Europe  
That is, we divide the tracing procedure in each debug run into a few periods and trace different sets of signals in each period.  ...  Trace-based debug solutions facilitate to eliminate design errors escaped from pre-silicon verification and have gained wide acceptance in the industry.  ...  INTRODUCTION Today's complex integrated circuit designs increasingly rely on post-silicon validation to eliminate bugs that escape from pre-silicon verification [2, 6, 8] .  ... 
doi:10.1109/date.2011.5763116 dblp:conf/date/LiuX11 fatcat:kmdrmunpnraw3eeb3iohjd7key

Automated trace signals identification and state restoration for improving observability in post-silicon validation

Ho Fai Ko, Nicola Nicolici
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
Embedded logic analysis has emerged as a powerful technique for identifying functional bugs during postsilicon validation, as it enables at-speed acquisition of data from the circuit nodes in real-time  ...  This paper introduces an automated method for improving the utilization of the on-chip storage, by identifying a small set of trace signals from which a large number of states can be restored using a compute-efficient  ...  during post-silicon validation.  ... 
doi:10.1145/1403375.1403689 fatcat:p4p4lcscyffkfejbd62vj6gioi

Scalable trace signal selection using machine learning

Kamran Rahmani, Prabhat Mishra, Sandip Ray
2013 2013 IEEE 31st International Conference on Computer Design (ICCD)  
A key problem in post-silicon validation is to identify a small set of traceable signals that are effective for debug during silicon execution.  ...  In this paper, we propose an efficient signal selection technique using machine learning to take advantage of simulation-based signal selection while significantly reducing the simulation overhead.  ...  RELATED WORK Limited observability of internal signals is the primary issue in post-silicon validation. Trace buffers have been widely used in post-silicon debug.  ... 
doi:10.1109/iccd.2013.6657069 dblp:conf/iccd/RahmaniMR13 fatcat:qpqvw4dozfd5dchy2qvs5ovyvu

On Reusing Test Access Mechanisms for Debug Data Transfer in SoC Post-Silicon Validation

Xiao Liu, Qiang Xu
2008 2008 17th Asian Test Symposium  
One of the main difficulties in post-silicon validation is the limited debug access bandwidth to internal signals.  ...  In this paper, we propose to reuse these precious TAM resources for real-time debug data transfer in post-silicon validation.  ...  ., Ltd. for his insightful comments to this work.  ... 
doi:10.1109/ats.2008.83 dblp:conf/ats/LiuX08 fatcat:kgpiuchbf5bf5dtmp5uolxacye

Interconnection fabric design for tracing signals in post-silicon validation

Xiao Liu, Qiang Xu
2009 Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09  
Post-silicon validation has become an essential step in the design flow of today's complex integrated circuits.  ...  These trace signals need to be transferred to on-chip buffers and/or off-chip trace ports for analysis.  ...  ACKNOWLEDGEMENTS This work was supported in part by the General Research Fund CUHK417406, CUHK417807, and CUHK418708 from Hong Kong SAR Research Grants Council, and in part by a grant N_CUHK417/08 from  ... 
doi:10.1145/1629911.1630006 dblp:conf/dac/LiuX09 fatcat:quzfhmwwqrhbvmj7xuykgoib34

Pruning-based trace signal selection algorithm

Kang Zhao, Jinian Bian
2011 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)  
"Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation". Proc.  ...  the bugs effectively -Know each state for each signal in the circuits -Enhance the visibility of the circuits 5 EDA Lab, Tsinghua University Dept.  ... 
doi:10.1109/aspdac.2011.5722267 dblp:conf/aspdac/ZhaoB11 fatcat:hx2iapmxqvc43bde7o3bg4doia

E-QED: Electrical Bug Localization During Post-silicon Validation Enabled by Quick Error Detection and Formal Methods [chapter]

Eshan Singh, Clark Barrett, Subhasish Mitra
2017 Lecture Notes in Computer Science  
During post-silicon validation, manufactured integrated circuits are extensively tested in actual system environments to detect design bugs.  ...  We present E-QED, a new approach that automatically localizes electrical bugs during post-silicon validation.  ...  These E-QED signature blocks are used during post-silicon validation to capture and compress the logic values of selected signals (signatures).  ... 
doi:10.1007/978-3-319-63390-9_6 fatcat:uo3imhrntzhwxm4hg3yilkxm7i

Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis

Joon-Sung Yang, Nur A. Touba
2012 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper, a technique is presented for selecting signals to observe during silicon debug. Internal signals are used to analyze, understand, and debug circuit misbehavior.  ...  An automated procedure to select which signals to observe is proposed to facilitate early detection of circuit malfunction and to enhance the utilization of hardware resources for storage.  ...  Unlike during pre-silicon verification, the accessibility and visibility of internal signals are very limited in post-silicon debug and hence this is the major challenge in the validation and debug of  ... 
doi:10.1109/tcad.2011.2171184 fatcat:wtnitgdxxfef7enehiuey4prpu
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