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On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon Validation

Xiao Liu, Qiang Xu
2010 2010 19th IEEE Asian Test Symposium  
Since tracing all speedpath-related signals can cause prohibited design for debug (DfD) overhead, we present an automated trace signal selection methodology that maximizes error detection probability under  ...  One of the most challenging problems in post-silicon validation is to identify those errors that cause prohibitive extra delay on speedpaths in the circuit under debug (CUD) and only expose themselves  ...  To the best of our knowledge, this is the first trace-based solution for debugging electrical errors in general logic circuits in post-silicon validation.  ... 
doi:10.1109/ats.2010.50 dblp:conf/ats/LiuX10 fatcat:lj4kere6kzd6zctoxerwodaxfq

Tutorial T10: Post - Silicon Validation, Debug and Diagnosis

Prabhat Mishra, Masahiro Fujita, Virendra Singh, Nagesh Tamarapalli, Sharad Kumar, Rajesh Mittal
2013 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems  
We will cover recent advances in observability enhancement through signal selection and low-overhead trace hardware design.  ...  Post-silicon validation is used to detect design flaws including the escaped functional errors as well as electrical faults.  ...  He currently manages the post silicon validation team which is involved in methodology development and tools for multi-core post silicon debug, besides driving validation for a variety of networking SoCs  ... 
doi:10.1109/vlsid.2013.145 dblp:conf/vlsid/MishraFSTKM13 fatcat:rszrw5prv5andmxnkuler3cd2m

Automated Debugging from Pre-Silicon to Post-Silicon [chapter]

Mehdi Dehbashi, Görschwin Fey
2014 Debug Automation from Pre-Silicon to Post-Silicon  
Diagnostic traces are proposed as an enhancement reducing debugging time and increasing diagnosis accuracy. The experimental results show the effectiveness of the approach in post-silicon debugging.  ...  This paper presents a generalized approach to automate debugging which can be used in different scenarios from design debugging to post-silicon debugging.  ...  AUTOMATED POST-SILICON DEBUGGING This section describes how the general automated debugging procedure is used for post-silicon debugging of design bugs and electrical bugs.  ... 
doi:10.1007/978-3-319-09309-3_4 fatcat:5vn3vvmc6bbydaen4t6v66bxum

Automated debugging from pre-silicon to post-silicon

Mehdi Dehbashi, Gorschwin Fey
2012 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)  
Diagnostic traces are proposed as an enhancement reducing debugging time and increasing diagnosis accuracy. The experimental results show the effectiveness of the approach in post-silicon debugging.  ...  This paper presents a generalized approach to automate debugging which can be used in different scenarios from design debugging to post-silicon debugging.  ...  AUTOMATED POST-SILICON DEBUGGING This section describes how the general automated debugging procedure is used for post-silicon debugging of design bugs and electrical bugs.  ... 
doi:10.1109/ddecs.2012.6219082 dblp:conf/ddecs/DehbashiF12 fatcat:q4xqraylffdanhhqdfh3dgm2q4

On signal tracing in post-silicon validation

Qiang Xu, Xiao Liu
2010 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)  
It is increasingly difficult to guarantee the first silicon success for complex integrated circuit (IC) designs. Post-silicon validation has thus become an essential step in the IC design flow.  ...  Trace-based debug solution, however, involves non-trivial design for debug overhead. How to conduct signal tracing effectively for bug elimination is therefore a challenging task for IC designers.  ...  A more challenging problem in post-silicon validation is to debug those electrical errors that only manifest themselves in certain electrical environment, which has not been explored much so far.  ... 
doi:10.1109/aspdac.2010.5419883 dblp:conf/aspdac/XuL10 fatcat:5ftlnjsgmbf6ro5vvlufbfvnhq

Observability-aware Directed Test Generation for Soft Errors and Crosstalk Faults

Kanad Basu, Prabhat Mishra, Priyadarsan Patra
2013 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems  
Post-silicon validation has emerged as an important component of any chip design methodology to detect both functional and electrical errors that have escaped the pre-silicon validation phase.  ...  In this paper, we explore the synergy between trace signal selection and observability-aware test generation to enable efficient detection of electrical errors including soft errors and crosstalk faults  ...  errors during post-silicon debug.  ... 
doi:10.1109/vlsid.2013.203 dblp:conf/vlsid/BasuMP13 fatcat:rq7drc5ctnfsjaj3mreqoiliai

A New Post-Silicon Debug Approach Based on Suspect Window

Jianliang Gao, Yinhe Han, Xiaowei Li
2009 2009 27th IEEE VLSI Test Symposium  
The main challenge for post-silicon debug is the observability of the internal signals. This paper exploits the fact that it is not necessary to observe the error free states.  ...  Bugs are tending to be unavoidable in the design of complex integrated circuits. It is imperative to identify the bugs as soon as possible by post-silicon debug.  ...  By tracing the selected signals in real-time, the errors, which are caused by the bugs in the circuit under debug, are collected into trace buffer.  ... 
doi:10.1109/vts.2009.35 dblp:conf/vts/GaoHL09 fatcat:xlmjqmiu4jbgbchalql6b6nsw4

Automating post-silicon debugging and repair

Kai-hui Chang, Igor L. Markov, Valeria Bertacco
2007 Computer-Aided Design (ICCAD), IEEE International Conference on  
Due to increasing semiconductor design complexity, more errors are escaping presilicon verification and being discovered only after manufacturing.  ...  As an alternative to traditional manual chip repair, the authors propose the FogClear methodology, which automates the postsilicon debugging process and thereby reduces IC development time and costs.  ...  For example, Intel developed an entirely new methodology for postdiagnosis of electrical bugs that affect signal delays. 3 Third, the observability of a silicon die's internal signals is extremely limited  ... 
doi:10.1109/iccad.2007.4397249 dblp:conf/iccad/ChangMB07 fatcat:7tb66p3rvnebzm44gptbfvhj5y

Post-silicon validation opportunities, challenges and recent advances

Subhasish Mitra, Sanjit A. Seshia, Nicola Nicolici
2010 Proceedings of the 47th Design Automation Conference on - DAC '10  
As a result, post-silicon validation is an emerging research topic with several exciting opportunities for major innovations in electronic design automation.  ...  Post-silicon validation is used to detect and fix bugs in integrated circuits and systems after manufacture.  ...  Acknowledgment This work is supported in part by the Semiconductor Research Corporation (SRC), the Gigascale Systems Research Center, one of six research centers funded under the Focus Center Research  ... 
doi:10.1145/1837274.1837280 dblp:conf/dac/MitraSN10 fatcat:hwycqj5eljfxbnszwn3zn5yjmy

Topological Ordering Signal Selection Technique for Internet of Things based on Combinational Gate for Visibility Enhancement

Agalya Rajendran, Muthaiah Rajappa
2020 Scalable Computing : Practice and Experience  
This shrinking market reduces the design automation validation process. Signal selection is the most effective and challenging technique in post-silicon validation and debug.  ...  Topology-based restoration method is proposed here to minimize the error detectionlatency which helps to select the trace signals with minimum error or even errorless.  ...  The authors sincerely thank DST-INSPIRE Fellowship and SASTRA Deemed University for providing a great support.  ... 
doi:10.12694/scpe.v21i1.1607 fatcat:gr5cgtbmyjdprnzifeup4qft2u

A case study of Time-Multiplexed Assertion Checking for post-silicon debugging

Ming Gao, Kwang-Ting Cheng
2010 2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)  
In this paper, we present a design-for-debug (DfD) techniquenamed Time-Multiplexed Assertion Checking (TMAC) --for post-silicon bug detection and isolation.  ...  Post-silicon debugging has become the least predictable and most labor-intensive step in the modern design flow at 65nm and below.  ...  Bug injection In post-silicon validation, functional errors and electrical bugs are the major targets.  ... 
doi:10.1109/hldvt.2010.5496657 dblp:conf/hldvt/GaoC10 fatcat:df2ytxj3b5gyzi4mczpimnqpkm

Bridging pre- and post-silicon debugging with BiPeD

Andrew DeOrio, Jialin Li, Valeria Bertacco
2012 Proceedings of the International Conference on Computer-Aided Design - ICCAD '12  
In post-silicon, this knowledge is used to detect errors by means of a reconfigurable hardware unit.  ...  Furthermore, pre-silicon verification and post-silicon validation methodologies are very different and share little information between them.  ...  First, the signals selected during pre-silicon verification for post-silicon observation have a critical impact on bug-finding capabilities.  ... 
doi:10.1145/2429384.2429403 dblp:conf/iccad/DeOrioLB12 fatcat:cdunae6j6rbspgiqi4rj2pcqzi

Post-silicon bug diagnosis with inconsistent executions

Andrew DeOrio, Daya Shanker Khudia, Valeria Bertacco
2011 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)  
During post-silicon validation, lightweight BPS hardware logs a compact encoding of observed signal activity over multiple executions of the same test: some passing, some failing.  ...  The complexity of modern chips intensifies verification challenges, and an increasing share of this verification effort is shouldered by post-silicon validation.  ...  The scope of signals available for observation during post-silicon validation varies with the quality of its debug infrastructure.  ... 
doi:10.1109/iccad.2011.6105414 dblp:conf/iccad/DeOrioKB11 fatcat:bbzbb3jjkngfllw47dev6dvof4

Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis

Joon-Sung Yang, Nur A. Touba
2012 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper, a technique is presented for selecting signals to observe during silicon debug. Internal signals are used to analyze, understand, and debug circuit misbehavior.  ...  Index Terms-Error propagation matrix, integer linear programming, signal observability, silicon debug.  ...  Unlike during pre-silicon verification, the accessibility and visibility of internal signals are very limited in post-silicon debug and hence this is the major challenge in the validation and debug of  ... 
doi:10.1109/tcad.2011.2171184 fatcat:wtnitgdxxfef7enehiuey4prpu

Post-silicon verification and debugging with control flow traces and patchable hardware

Masahiro Fujita
2012 2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)  
In this paper we show three methods for postsilicon verification and debugging with control-flow analysis.  ...  By recognizing abnormal transitions, which is basically control flow analysis, both logical and electrical errors can be efficiently detected during postsilicon debug.  ...  POST-SILICON VERIFICATION BY TRACING/ANALYZING COMMUNICATIONS AMONG CORES Here we introduce a method for debugging communications in SoCs at transaction level [2] .  ... 
doi:10.1109/hldvt.2012.6418250 dblp:conf/hldvt/Fujita12 fatcat:unnymogrqvfa5mvbftecngryyq
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