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Towards a traceability model in a MARTE-based methodology for real-time embedded systems

Hung Le Dang, Hubert Dubois, Sébastien Gérard
2008 Innovations in Systems and Software Engineering  
Requirement meta-model Our solution: a triptych vision towards a separation of concerns but in the UML-based formalism A process that can be connected to heterogeneous formalisms for solution modeling  ...  , the 27 th 2008 DTSI Traceability in the models with MARTE A clear connexion between requirements and models A specific UML profile for embedded systems: MARTE For RT/ES specificities: real-time  ... 
doi:10.1007/s11334-008-0053-4 fatcat:4rjyx7cewrgghdlj3rcixab4tq

Generic Methodology for Formal Verification of UML Models

K.H. Kochaleema, G. Santhosh Kumar
2022 Defence Science Journal  
Our approach proposes a UML-based formal verification process utilising functional and behavioural modelling artifacts of UML.  ...  This paper discusses a Unified Modelling Language (UML) based formal verification methodology for early error detection in the model-based software development cycle.  ...  Currently, UML models are used for modelling all kinds of systems, including real time and embedded systems.  ... 
doi:10.14429/dsj.72.17228 fatcat:oiofljfysjcazcvqp6uwgjx3ni

Design validation of embedded dependable systems

A. Bondavalli, A. Fantechi, D. Latella, L. Simoncini
2001 IEEE Micro  
. • The evolution and verification of product and process designs. The quality of a product design depends on the quality of the process that produces it.  ...  The current disciplines of hardware, firmware, software, and application engineering-commonly considered as separate-must evolve toward a system engineering discipline.  ...  Formal verification Formal verification is a hot topic especially for the development of dependable embedded systems.  ... 
doi:10.1109/40.958699 fatcat:wghik64werc27lhq3tyumg2xn4


Deepak Arora .
2014 International Journal of Research in Engineering and Technology  
Model based verification has been a key area to be explored to establish the model consistency and validation formalization.  ...  This research work emphasises the development of novel techniques for the verification and validation of different UML models.  ...  RQ4-What is the need of Formalization of UML Diagrams? Formalization of UML has become a prominent domain of research for the last few years.  ... 
doi:10.15623/ijret.2014.0322016 fatcat:tbmpeep2g5gofhylq5d6dyxmta

UML-based modeling and formal verification of security protocols

Sara Mota, Benjamin Fontan
2005 Proceedings of the 2005 ACM conference on Emerging network experiment and technology - CoNEXT'05  
This paper presents an ongoing work on modeling and formal verification of a secure group communication protocol using TURTLE [APR04] , a UML profile based on the formal language RT-LOTOS.  ...  TTool also enables the edition of TURTLE diagrams. The TURTLE profile has been defined for the specification, design and verification of real-time distributed systems.  ... 
doi:10.1145/1095921.1095981 dblp:conf/conext/MotaF05 fatcat:bpqfmq2hv5dflg6pa7qryes77a

Correct Development of Embedded Systems [chapter]

Susanne Graf, Jozef Hooman
2004 Lecture Notes in Computer Science  
This paper provides an overview on the approach of the IST OMEGA project for the development of correct software for embedded systems based on the use of UML as modelling language.  ...  The main contributions of the project are the definition of a useful subset of UML and some extensions, a formal dynamic semantics integrating all notations and a tool set for the validation of models  ...  Formal verification: Little tool support exists so far for the formal verification of all aspects of this kind of systems.  ... 
doi:10.1007/978-3-540-24769-2_21 fatcat:fvsqeoqndjbnbfnktiof35ytl4

Modelling a moving block train control system: different techniques and tools

Franco Mazzanti
2019 Zenodo  
Invited talk - "Modelling a moving block train control system: different techniques and tools" at DisCoRail 2019 - International Workshop on Distributed Computing in Future Railway Systems- Lyngby, 17  ...  Formal Verification of Systems Compositions DiscoRail 2019 UMC overview DiscoRail 2019 towards PROB t1 t2 t1 = PRE ... END t2 = PRE ...  ...  , MA is resent three times ... Timed/Probabilistic Processes (Uppaal) Event B (ProB) UML based design (UMC) Process Algebras (CADP) Statecharts (Simulink) DiscoRail 2019  ... 
doi:10.5281/zenodo.3518006 fatcat:q6mpdjr4znbe3dbise3w36625a

An Emerging Need for a New Software Engineering Method

Isabelle Perseil, Laurent Pautet
2009 2009 14th IEEE International Conference on Engineering of Complex Computer Systems  
The Unified Process is analyzed and revisited in order to support the new types of requirements that we have identified to require the integration of formal methods, a proof-based system engineering approach  ...  This paper presents the issues related to the lack of method in the field of software engineering for real-time systems (in particular, avionic systems).  ...  lifecycle is obvious • It is missing specially because critical real-time systems need to be formally checked • to have a support of formal languages in the earliest steps of the design -13-AAA Strong  ... 
doi:10.1109/iceccs.2009.40 dblp:conf/iceccs/PerseilP09 fatcat:uqpjsirlwzc23gyi3ncfs2itbe

Specification and Formal Verification of Temporal Properties of Production Automation Systems [chapter]

Stephan Flake, Wolfgang Müller, Ulrich Pape, Jürgen Ruf
2004 Lecture Notes in Computer Science  
We introduce the formal semantics of RT-OCL based on a formal model of UML Class and State Diagrams and provide a mapping to temporal logics.  ...  This article describes our approach for the specification and verification of production automation systems with real-time properties.  ...  In the final phase, the GRASP project received partial contributions from the DFG Special Research Initiative 614 'Selbstoptimierende Systeme des Maschinenbaus'.  ... 
doi:10.1007/978-3-540-27863-4_13 fatcat:dyzjgzcdffauxh74wx52rd2yha

A Dynamic Assertion-Based Verification Platform for Validation of UML Designs [chapter]

Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, Partha Pratim Chakrabarti, S. Ramesh, P. Vignesh V. Ganesan
2008 Lecture Notes in Computer Science  
For quite some time, the Unified Modeling Language (UML) [5] has been adopted by designers of safety critical control systems such as automotive and aviation control.  ...  In view of the growing popularity of modelbased development, we believe that the verification methodology presented in this paper is of immediate practical value to the UML-based design community.  ...  The Verification Engine The main idea of DPV is based on examining the responses of the system under test during simulation.  ... 
doi:10.1007/978-3-540-88387-6_18 fatcat:2qpqt7htivhvhftxmv76l2voxi

A dynamic assertion-based verification platform for validation of UML designs

A. Banerjee, S. Ray, P. Dasgupta, P. P. Chakrabarti, S. Ramesh, P. Vignesh, V. Ganesan
2012 Software engineering notes  
For quite some time, the Unified Modeling Language (UML) [5] has been adopted by designers of safety critical control systems such as automotive and aviation control.  ...  In view of the growing popularity of modelbased development, we believe that the verification methodology presented in this paper is of immediate practical value to the UML-based design community.  ...  The Verification Engine The main idea of DPV is based on examining the responses of the system under test during simulation.  ... 
doi:10.1145/2088883.2088891 fatcat:pjopnfbvu5cqzgeajqw65psesi

SVERTS – Specification and Validation of Real-Time and Embedded Systems [chapter]

Susanne Graf, Øystein Haugen, Ileana Ober, Bran Selic
2005 Lecture Notes in Computer Science  
This paper presents an overview on the workshop on Specification and Validation of Real-time and embedded Systems that has taken place for the second time in association with the UML 2004 conference.  ...  The main themes discussed at this years workshop concerned modeling of real-time features with the perspective of validation as well as some particular validation issues.  ...  The authors of this contribution propose a formal support of UML model-based verification by mapping a subset of UML to time-extended B specifications [Abr96] .  ... 
doi:10.1007/978-3-540-31797-5_4 fatcat:a5mxsl5sw5buthatvzfexpradm

Specification, verification, and quantification of security in model-based systems

Samir Ouchani, Mourad Debbabi
2015 Computing  
In this paper, we review the state-of-the-art related to security specification, verification, and quantification for software and systems that are modeled by using UML or SysML language.  ...  The reviewed work fall into the field of secure software and systems engineering that aims at fulfilling the security as an afterthought in the development of secure systems.  ...  Those research directions are considered as hot research topics in security and formal verification in both software and hardware modeling for the next years.  ... 
doi:10.1007/s00607-015-0445-x fatcat:yuifxclfgfcmhoxjfpateksysq

An approach to refinement checking of SysML requirements

Denis Makartetskiy, Riccardo Sisto
2011 ETFA2011  
This work shows efforts towards integrating embedded systems modeling with verification measures, namely, with refinement checking (checking whether a system description is really an implementation of  ...  We show how such verification can be done automatically with the help of externally implemented tools.  ...  Taking some of the results coming from this line of research, the distinguishing characteristic of our work is to apply formal verification of UML statemachines in the context of requirements verification  ... 
doi:10.1109/etfa.2011.6059147 dblp:conf/etfa/MakartetskiyS11 fatcat:2p33gvd5jffrzpzwhqitx33wna

Verifying and Monitoring UML Models with Observer Automata: A Transformation-Free Approach

Valentin Besnard, Ciprian Teodorov, Frederic Jouault, Matthias Brun, Philippe Dhaussy
2019 2019 ACM/IEEE 22nd International Conference on Model Driven Engineering Languages and Systems (MODELS)  
The authors especially thank David Olivier for his advice and industrial feedback.  ...  Second, the use of formal verification techniques remains a complex task for system engineers that do not have a formal background.  ...  Future work also includes the integration of other model-based specification formalism such as Property Sequence Chart (PSC) [AIP07] based on an extension of UML 2.0 interaction diagrams.  ... 
doi:10.1109/models.2019.000-5 dblp:conf/models/BesnardTJ0D19a fatcat:q2gkzqxjrjc3pfzz4s4vojih3e
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