Filters








855 Hits in 4.7 sec

Optimizing electronic standard cell libraries for variability tolerance through the nano-CMOS grid

J. A. Walker, R. Sinnott, G. Stewart, J. A. Hilder, A. M. Tyrrell
2010 Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences  
The goal is to extract high-speed and low-power circuits which are more tolerant of the random fluctuations that will be prevalent in future technology nodes.  ...  The authors would like to thank all the partners in the Nano-CMOS project, especially the DMG at University of Glasgow for providing the variability-enhanced models and the randomspice application.  ...  Nano-CMOS is an EPSRC-funded project (ref: EP/E001610/1).  ... 
doi:10.1098/rsta.2010.0150 pmid:20643688 fatcat:5rda3jxstbcmjkbuxpqkhvop5m

PAnDA: A Reconfigurable Architecture that Adapts to Physical Substrate Variations

James Alfred Walker, Martin A. Trefzer, Simon J. Bale, Andy M. Tyrrell
2013 IEEE transactions on computers  
As these transistors reduce in size intrinsic variability becomes more of a problem and to reliably create electronic designs according to specification time consuming statistical simulations become necessary  ...  ., not restricted to reducing stochastic variability, power consumption or increasing speed, the same mechanisms can also enhance the device's fault tolerant abilities in the case of component degradation  ...  Second, the design most affected by intrinsic variability has been SRAM [6] .  ... 
doi:10.1109/tc.2013.59 fatcat:df2nxtq4wvblxdhq3ool4yhyhy

A programmable analogue and digital array for bio-inspired electronic design optimization at nano-scale silicon technology nodes

Martin A. Trefzer, James A. Walker, Andy M. Tyrrell
2011 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR)  
Unfortunately, in order to reliably create electronic designs according to specification time-consuming statistical simulations become necessary due to effects of intrinsic variability.  ...  This paper describes an adaptive, evolvable architecture that allows for correction and optimisation of circuits directly in hardware using bio-inspired techniques.  ...  Until now the design most affected by intrinsic variability has been SRAM [6] .  ... 
doi:10.1109/acssc.2011.6190276 dblp:conf/acssc/TrefzerWT11 fatcat:2prkcdgffvdpjp4dsyh7h6ppya

Rebooting Neuromorphic Hardware Design – A Complexity Engineering Approach [article]

Natesh Ganesh
2020 arXiv   pre-print
New emerging devices like memristors, atomic switches, etc have shown tremendous potential to replace CMOS-based circuits but have been hindered by multiple challenges with respect to device variability  ...  A reservoir computing example is used to understand the specific changes that would accompany in moving towards a complexity engineering approach.  ...  it feasible and profitable.  ... 
arXiv:2005.00522v2 fatcat:66m4bc2dyjf7fhqzfczwwxva4e

The future of solid-state electronics

William F. Brinkman, Mark R. Pinto
2002 Bell Labs technical journal  
Interconnection With the increasing complexities of designs and larger chip sizes, interconnect technology has evolved into a primary concern.  ...  The case seems very convincing that the industry will return to the situation in which device-to-device variations will be the dominant factor in determining the feasibility of further progress on monolithic  ... 
doi:10.1002/bltj.2083 fatcat:auwjdokrmbahxc7op2jksmsxfi

2001 technology roadmap for semiconductors

A. Allan, D. Edenfeld, W.H. Joyner, A.B. Kahng, M. Rodgers, Y. Zorian
2002 Computer  
Does directing the industry momentum toward DFT-based designs to decrease product test cost make functional test go away?  ...  Feasibility of future technology nodes will depend on sharing challenges within the industry as a whole.  ... 
doi:10.1109/2.976918 fatcat:mv3q7f3l2zfjng2i5rvipkdhsi

2003 technology roadmap for semiconductors

D. Edenfeld, A.B. Kahng, M. Rodgers, Y. Zorian
2004 Computer  
This update to the 2001 ITRS Roadmap shows the industry shifting its focus toward systems on chip, wireless computing, and mobile applications.  ...  System-on-chip (SoC) and system-in-package (SiP) designs that incorporate building blocks from multiple sources are supplanting in-house, single-source chip designs.  ...  Researchers also can use mixed-signal design analysis to estimate design needs and feasibility for future applications and new markets.  ... 
doi:10.1109/mc.2004.1260725 fatcat:eqstk5zzbzfkbl6upd2jjc4f4m

Challenges of evolvable hardware: past, present and the path to a promising future

Pauline C. Haddow, Andy M. Tyrrell
2011 Genetic Programming and Evolvable Machines  
Evolvable Hardware (EH) is a field of evolutionary computation (EC) that focuses on the embodiment of evolution in a physical media.  ...  If EH could achieve even a small step in natural evolution's achievements, it would be a significant step for hardware designers.  ...  evolution process) • Typically evolved systems do show levels of fault tolerance not seen in designed systems (again typical of biological systems) • They may be designed to be adaptable to environment  ... 
doi:10.1007/s10710-011-9141-6 fatcat:5jal32pzizc2pclgoqggchuiz4

Introduction to mm-Wave Silicon Devices, Circuits, and Systems [chapter]

Ali M. Niknejad, Hossein Hashemi
2008 Series on Integrated Circuits and Systems  
As Moore's Law has recently pushed the f t and f max of CMOS transistors above 100 GHz, an all-CMOS solution at 60 GHz is feasible.  ...  And while Moore's Law has enabled CMOS mm-wave circuit design, CMOS is by far not optimized for mm-wave performance.  ... 
doi:10.1007/978-0-387-76561-7_1 fatcat:ddt7wmxhpvewxpnvo2nbxmtviy

Technologies for Cofabricating MEMS and Electronics

G.K. Fedder, R.T. Howe, Tsu-Jae King Liu, E.P. Quevy
2008 Proceedings of the IEEE  
University research efforts have proven the feasibility of this approach, and recent developments have been made by companies and large industrial laboratories.  ...  Although custom processes that interleave MEMS and electronic fabrication steps are feasible and have been commercialized, the trend in recent developments is toward more modular approaches.  ... 
doi:10.1109/jproc.2007.911064 fatcat:4cgy5gufijhnzjwsykka5ltdkq

Spintronic Nanodevices for Bioinspired Computing

Julie Grollier, Damien Querlioz, Mark D. Stiles
2016 Proceedings of the IEEE  
We review the different approaches that have been proposed, the recent advances in this direction, and the challenges toward fully integrated spintronics complementary metal-oxide-semiconductor (CMOS)  ...  This approach is feasible though challenging.  ...  While most neural network models are very tolerant to variability between components (i.e., different behaviors for different neurons and synapses), the quality of computation degrades rapidly when the  ... 
doi:10.1109/jproc.2016.2597152 pmid:27881881 pmcid:PMC5117478 fatcat:2627tylxtzauvim5uc57znskgi

Spintronic nano-devices for bio-inspired computing [article]

Julie Grollier, Damien Querlioz, Mark D. Stiles
2016 arXiv   pre-print
We review the different approaches that have been proposed, the recent advances in this direction, and the challenges towards fully integrated spintronics-CMOS (Complementary metal - oxide - semiconductor  ...  This approach is feasible though challenging.  ...  While most neural network models are very tolerant to variability between components (i.e. different behaviors for different neurons and synapses), the quality of computation degrades rapidly when the  ... 
arXiv:1606.07700v2 fatcat:h5eorqvne5d4hc4gvyj2pystlm

On Evolvable Hardware [chapter]

G. W. Timothy Gordon, J. Peter Bentley
2002 Studies in Fuzziness and Soft Computing  
This he called intrinsic evolvable hardware.  ...  of fault tolerant systems and • Innovation in poorly understood design spaces.  ... 
doi:10.1007/978-3-7908-1783-6_8 fatcat:a3hruil2szcw7lwtuhsjo5q6ey

Device scaling limits of Si MOSFETs and their application dependencies

D.J. Frank, R.H. Dennard, E. Nowak, P.M. Solomon, Y. Taur, Hon-Sum Philip Wong
2001 Proceedings of the IEEE  
He is currently engaged in the pursuit of sub-one-volt device designs and continues work on high-speed CMOS device design.  ...  He has contributed to numerous high-speed CMOS projects from 1.0-m to 0.1-m scales.  ...  To explore in more detail the limit of bulk (and PD-SOI) CMOS scaling, we present a feasible design for 25-nm (channel length) bulk CMOS without complete scaling of oxide thickness and power supply voltage  ... 
doi:10.1109/5.915374 fatcat:r4tvpqmqofgrfg2zuxhrtjwpqe

Stacked strained silicon transistors for low-power high-performance circuit applications

H. Ramakrishnan, S. Shedabale, G. Russell, A. Yakovlev
2008 2008 58th Electronic Components and Technology Conference  
The impact of process variability on particular design parameters on several strained-Si circuits was investigated using two statistical methods, namely Design of Experiments (DOE) and Response Surface  ...  Unfortunately, the power dissipation resulting from the use of conventional CMOS technology in this area is becoming a critical design issue.  ...  The microelectronics industry is striving towards the integration of billions of transistors onto a single chip.  ... 
doi:10.1109/ectc.2008.4550224 fatcat:ijp5zrokxbebrlv5w2b7ua2c44
« Previous Showing results 1 — 15 out of 855 results