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Page 397 of Computational Linguistics Vol. 17, Issue 4 [page]

1991 Computational Linguistics  
by implementing a sort of parallel search, working back from the right of the network toward its root.  ...  In the example above we would have had to note that genfeat = c, V cz and to retain this information for future checking. 3.3 Overview of the Checking Algorithm Our consistency checking algorithm works  ... 

A parallelized layered QC-LDPC decoder for IEEE 802.11ad

Alexios Balatsoukas-Stimming, Nicholas Preyss, Alessandro Cevrero, Andreas Burg, Christoph Roth
2013 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)  
The decoding algorithm is equivalent to a nonparallelized layered decoder and, thus, retains its favorable convergence characteristics, which are known to be superior to those of flooding schedule based  ...  We present a doubly parallelized layered quasi-cyclic lowdensity parity-check decoder for the emerging IEEE 802.11ad multigigabit wireless standard.  ...  highly efficient decoding algorithms.  ... 
doi:10.1109/newcas.2013.6573590 dblp:conf/newcas/Balatsoukas-Stimming13 fatcat:s6tjzqco25d2pgtrcrwxjbpuzm

Property Directed Reachability for Automated Planning

M. Suda
2014 The Journal of Artificial Intelligence Research  
While originally conceived as a model checking algorithm for hardware circuits, it has already been successfully applied in several other areas.  ...  We show that most standard encoding schemes of planning into SAT can be directly used to turn PDR into a planning algorithm.  ...  With awareness of the well-known equivalence between model checking and automated planning, the aim of this work is to investigate PDR from the planning perspective.  ... 
doi:10.1613/jair.4231 fatcat:d5v5z54brvfepbbiwrd6s7dmd4

Page 5368 of Mathematical Reviews Vol. , Issue 90I [page]

1990 Mathematical Reviews  
Kruskal, Efficient parallel algorithms: theory and practice (pp. 77-79); Tom Leighton [Frank Thomson Leighton], What is the right model for design- ing parallel algorithms?  ...  incremental attribute evaluation (pp. 483-491); Peter Ruzitka, On efficiency of interval routing algorithms (pp. 492-500); Peter RuZitka and Igor Privara, An almost linear Robinson unification algorithm  ... 

ReGiS: Regular Expression Simplification via Rewrite-Guided Synthesis [article]

Jordan Schmerge, Miles Claver, Jackson Garner, Jake Vossen, Jedidiah McClurg
2021 arXiv   pre-print
Equality saturation is an alternative approach which allows efficient construction and maintenance of expression equivalence classes generated by rewrite rules, but the procedure may not reach saturation  ...  We demonstrate the flexibility and practicality of our approach by applying ReGiS to regular expression denial of service (ReDoS) attack prevention.  ...  Algorithms which exploit equivalence relations and utilize efficient disjoint-set data structures can offer further improvement [21, 6] , but the overhead of maintaining these data structures can limit  ... 
arXiv:2104.12039v2 fatcat:urxthgmb7jcxnmw3dsa2ns32xu

Techniques for Distributed Reachability Analysis with Partial Order and Symmetry based Reductions [article]

Janardan Misra, Suman Roy
2009 arXiv   pre-print
In this work we propose techniques for efficient reachability analysis of the state space (e.g., detection of bad states) using a combination of partial order and symmetry based reductions in a distributed  ...  The proposed techniques are focused towards explicit state space enumeration based model-checkers like SPIN.  ...  The key part of such an algorithm is the distributed checking of the ample conditions.  ... 
arXiv:0901.0179v1 fatcat:7anazzroereh7jdxrrteki5vaq

Author Index

2008 2008 IEEE International Symposium on Parallel and Distributed Processing  
Automatic Generation of a Parallel Sorting Algorithm Efficient Software Checking for Fault Tolerance Garzia, Fabio Implementation of a Floating-point Matrix-vector Multiplication on a Reconfigurable Architecture  ...  Automatic Generation of a Parallel Sorting Algorithm García, José M.  ... 
doi:10.1109/ipdps.2008.4536576 fatcat:7unikf5ywjhjtdd6xtrmcom3gq

Scalable conditional equivalence checking: An automated invariant-generation based approach

Jason Baumgartner, Hari Mony, Michael Case, Jun Sawada, Karen Yorav
2009 2009 Formal Methods in Computer-Aided Design  
Sequential equivalence checking (SEC) technologies, capable of demonstrating the behavioral equivalence of two designs, have grown dramatically in capacity over the past decades.  ...  The ability to efficiently identify and leverage internal equivalence points to reduce the domain of the overall SEC problem is central to SEC scalability.  ...  Of these, bounded model checking falsified 357, whereas our bit-parallel simulator falsified 242,330: a ratio of 1:679.  ... 
doi:10.1109/fmcad.2009.5351131 dblp:conf/fmcad/BaumgartnerMCSY09 fatcat:abtilmgzqzhplhpcf7pbpjngjy

Page 1053 of Mathematical Reviews Vol. , Issue 91B [page]

1991 Mathematical Reviews  
time of a parallel C.  ...  Lipton, Efficient checking of compu- tations (pp. 207-215); Luc Longpré and Alan L. Selman, Hard promise problems and nonuniform complexity (pp. 216-226); K. Mehlhorn, St. Meiser and C.  ... 

Powerful Equivalence Checking in the Bank Supply Process

Giuseppe De Ruvo, Antonella Santone, Domenico Raucci
2014 2014 IEEE World Congress on Services  
We explore the applicability of equivalence checking to validation of Business Processes described by the aid of Workflow Management systems.  ...  Equivalence checking is a powerful formal technique to improve the quality of computer and software systems. It is usually employed to verify the correctness in a model-based design.  ...  For equivalence checking algorithms with minimal space complexity are of particular interest. Two algorithmic families can be considered to perform the equivalence checking.  ... 
doi:10.1109/services.2014.25 dblp:conf/services/RuvoSR14 fatcat:h7d4zl3ipfb2rn7xwb7s356rna

Automated Hypersafety Verification [chapter]

Azadeh Farzan, Anthony Vandikas
2019 Lecture Notes in Computer Science  
We propose an algorithm based on a counterexampleguided refinement loop that simultaneously searches for a reduction and a proof of the correctness for the reduction.  ...  The key observation is that constructing a proof for a small representative set of the runs of the product program (i.e. the product of the several copies of the program by itself), called a reduction,  ...  This refinement loop relies on an efficient algorithm for proof checking based on the antichain method of [8] , and strong theoretical progress guarantees.  ... 
doi:10.1007/978-3-030-25540-4_11 fatcat:zecykuzxpberxkpva27ac7okvy

Gradient Projection Decoding of LDPC Codes

Christos Kasparis, Barry Evans
2007 IEEE Communications Letters  
The followed approach involves reformulating the parity check equations using nonlinear functions of a specific form, defined over ρ , where ρ denotes the check node degree.  ...  The gradient projection algorithm is then used for searching for a valid codeword that lies in the vicinity of the channel observation.  ...  Elias Gyftodimos from the Computing Science Department, University of Aberdeen, for his valuable comments and suggestions.  ... 
doi:10.1109/lcomm.2007.061780 fatcat:cpvxehhfvjhorodjz3c7dgjrdq

Toward Formal-Methods Oecumenism?

F. Kordon, L. Petrucci
2006 IEEE Distributed Systems Online  
But, if model checking remains as efficient as what you can get from a Promela program, the model itself only offers basic constructs to handle parallelism.  ...  There are lots of stories of theorem provers or equivalent techniques such as B, Z, or other algebraic methods solving problems.  ... 
doi:10.1109/mdso.2006.47 fatcat:mrol4fgzlnarxculyzbwcxvbfe

A highly parallel Turbo Product Code decoder without interleaving resource

Camille Leroux, Christophe Jego, Patrick Adde, Michel Jezequel, Deepak Gupta
2008 2008 IEEE Workshop on Signal Processing Systems  
Syntheses show the better efficiency of such an architecture compared with existing previous solutions.  ...  This architecture includes a full-parallel SISO decoder able to process n symbols in one clock period.  ...  Towards a maximal parallelism rate Previous synthesis results showed the better efficiency of parallel architecture compared with duplicated architectures.  ... 
doi:10.1109/sips.2008.4671728 dblp:conf/sips/LerouxJAJG08 fatcat:wdhhflodljb6jgvlqhui7yil7a

Page 1898 of Mathematical Reviews Vol. , Issue 81E [page]

1981 Mathematical Reviews  
The structure imposed by the series-parallel constraint has useful implications for a design language translator in the areas of timing, bus assignment and conflict checking.  ...  Starting with the denotational semantics of Lucid, an equivalent operational semantics is derived, and from it the design of compiling algorithms.  ... 
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