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Towards Time-Predictable Data Caches for Chip-Multiprocessors [chapter]

Martin Schoeberl, Wolfgang Puffitsch, Benedikt Huber
2009 Lecture Notes in Computer Science  
in a prototype chip-multiprocessor system.  ...  Future embedded systems are expected to use chip-multiprocessors to provide the execution power for increasingly demanding applications.  ...  We are targeting chip-multiprocessor systems with private caches, even for accesses to constants, to keep the individual tasks time-predictable.  ... 
doi:10.1007/978-3-642-10265-3_17 fatcat:dy2urosnlvbqxmmtuapdas3vna

Study of Various Factors Affecting Performance of Multi-Core Processors

Nitin Chaturvedi, Gurunarayanan S
2013 International Journal of Distributed and Parallel systems  
As Chip Multiprocessor system (CMP) become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single chip.  ...  64 to 2048 entries on a 4 node, 8 node 16 node and 64 node Chip multiprocessor which in turn presents an open area of research on multicore processors with private/shared last level cache as the future  ...  The trend towards more integration of resources on a single chip is becoming more apparent in CMP designs where multiprocessor systems are built on a single chip.  ... 
doi:10.5121/ijdps.2013.4404 fatcat:ipcaejvdybaipejw5ehavdham4

Towards a Java multiprocessor

Christof Pitter, Martin Schoeberl
2007 Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems - JTRES '07  
This paper describes the first steps towards a Java multiprocessor system on a single chip for embedded systems.  ...  The chip multiprocessing (CMP) system consists of a homogeneous set of processing elements and a shared memory. Each processor core is based on the Java Optimized Processor (JOP).  ...  Acknowledgement The TPCM-project received support from the Austrian FIT-IT SoC initiative, funded by the Austrian Ministry for Traffic, Innovation and Technology (BMVIT) and managed by the Austrian Research  ... 
doi:10.1145/1288940.1288962 dblp:conf/jtres/PitterS07 fatcat:kymjieugtfg4va4l375ek256ue

Tuning data replication for improving behavior of MPSoC applications

O. Ozturk, M. Kandemir, M. J. Irwin, I. Kolcu
2004 Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04  
Maintaining cache coherence can be very costly for on-chip multiprocessors from an energy perspective.  ...  Observing this, we propose a compiler-directed strategy that replicates array data in cache memories of its potential consumer processors at the time the data is brought from off-chip memory.  ...  This brings an important sideadvantage in terms of execution time predictability since it is easier to predict execution time with simple processors without sophisticated prediction/speculation logic (  ... 
doi:10.1145/988952.988994 dblp:conf/glvlsi/OzturkKIK04 fatcat:w35sv54d5zbjdlc36m5jywsib4

The case for a single-chip multiprocessor

Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson, Kunyung Chang
1996 Proceedings of the seventh international conference on Architectural support for programming languages and operating systems - ASPLOS-VII  
Single-chip multiprocessor architectures have the advantage in that they offer localized implementation of a high-clock rate processor for inherently sequential applications and low latency interprocessor  ...  This paper shows that in advanced technologies it is possible to implement a single-chip multiprocessor in the same area as a wide issue superscalar processor.  ...  The application pull towards a single-chip multiprocessor arises because these two classes of applications require different execu- tion models.  ... 
doi:10.1145/237090.237140 dblp:conf/asplos/OlukotunNHWC96 fatcat:elff5i3fubd2thsx66mc56tfsu

The case for a single-chip multiprocessor

Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson, Kunyung Chang
1996 SIGPLAN notices  
Single-chip multiprocessor architectures have the advantage in that they offer localized implementation of a high-clock rate processor for inherently sequential applications and low latency interprocessor  ...  This paper shows that in advanced technologies it is possible to implement a single-chip multiprocessor in the same area as a wide issue superscalar processor.  ...  The application pull towards a single-chip multiprocessor arises because these two classes of applications require different execu- tion models.  ... 
doi:10.1145/248209.237140 fatcat:g2plt23b3vgtzii32m255gzt5i

The case for a single-chip multiprocessor

Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson, Kunyung Chang
1996 ACM SIGOPS Operating Systems Review  
Single-chip multiprocessor architectures have the advantage in that they offer localized implementation of a high-clock rate processor for inherently sequential applications and low latency interprocessor  ...  This paper shows that in advanced technologies it is possible to implement a single-chip multiprocessor in the same area as a wide issue superscalar processor.  ...  The application pull towards a single-chip multiprocessor arises because these two classes of applications require different execu- tion models.  ... 
doi:10.1145/248208.237140 fatcat:haj7x4knvfeftdhte35vryl7ry

Predictive modeling based power estimation for embedded multicore systems

Sriram Sankaran
2016 Proceedings of the ACM International Conference on Computing Frontiers - CF '16  
In this work, a statistical approach that models the impact of the individual cores and memory hierarchy on overall power consumed by Chip Multiprocessors is developed using Performance Counters.  ...  Evaluation of the model shows a strong correlation between core-level activity and power consumption and that the model predicts power consumption for newer observations with minimal errors.  ...  [18] developed regression models to predict the performance of Chip Multiprocessors.  ... 
doi:10.1145/2903150.2911714 dblp:conf/cd/Sankaran16 fatcat:laqycfmrmrbzjaj5eti6y6oezi

Performance and power impact of issue-width in chip-multiprocessor cores

M. Ekman, P. Stenstrom
2003 2003 International Conference on Parallel Processing, 2003. Proceedings.  
In chip-multiprocessors (CMPs), the number of cores and the issue width of each core presents an important design trade-off to balance the amount of TLP and ILP between multi-threaded and single-threaded  ...  Despite the fact that several simple cores are advantageous for well-behaved parallel applications, e.g.  ...  Additionally, we are grateful to Fredrik Dahlgren at Ericsson Mobile Platforms for valuable input and ideas for this study. Finally, thanks to Jianwei Chen for providing the SimWattch environment.  ... 
doi:10.1109/icpp.2003.1240600 dblp:conf/icpp/EkmanS03 fatcat:d4rmjgrodbfafi3qtzax3uw2xu

Scaling up the Atlas chip-multiprocessor

P.G. Sassone, D.S. Wills
2005 IEEE transactions on computers  
Atlas, a dynamically multithreading chip-multiprocessor (CMP), gains little complexity as processing elements are added.  ...  As transistor integration grows toward one billion transistors on a chip, however, the question of Atlas scalability emerges: Though a chip with more processing elements is technically feasible, do silicon  ...  Only some of this prior work utilizes chip-multiprocessors for dynamic multithreading despite their simpler design, easier validation, and shorter wire lengths [6] .  ... 
doi:10.1109/tc.2005.12 fatcat:4aei7qcbvjg3phzhiorzuqqeuu

Millimeter wave wireless network on chip using deep reinforcement learning

Suraj Jog, Zikun Liu, Antonio Franques, Vimuth Fernando, Haitham Hassanieh, Sergi Abadal, Josep Torrellas
2020 Proceedings of the SIGCOMM '20 Poster and Demo Sessions  
Wireless Network-on-Chip (NoC) has emerged as a promising solution to scale chip multi-core processors to hundreds of cores.  ...  Our results show that NeuMAC can quickly adapt to NoC traffic to provide significant gains in terms of latency and overall execution time, improving the execution time by up to 1.69× -3.74×.  ...  Millimeter Wave Wireless Network on Chip Using Deep Reinforcement Learning SIGCOMM '20 Posters, Aug 10-14, 2020, Virtual Event, USA  ... 
doi:10.1145/3405837.3411396 fatcat:jdvjzhf5l5aq7cu2ps2jcqcrza

Efficient Energy and Power Consumption of 3-D Chip Multiprocessor with NUCA Architecture

D. Priya, J. Arunarasi, A. Arul Mary
2016 Indian Journal of Science and Technology  
The predictable lower-level caches have the best ever access time among the entire the sub arrays, although such uniform cache access don't make the use of differences in latencies of the entire sub arrays  ...  This larger cache memory increases overall wire delays across the chip due to very bulky latencies.  ...  Also 3-D integration uses a last-level on-chip cache to permit stacking multiple small blocks of IC which is unrelated memories against a multiprocessor die.  ... 
doi:10.17485/ijst/2016/v9i2/85815 fatcat:u6rufetkqrg3bi6vvvxdbmrz4u

Chip Multiprocessor Design Space Exploration through Statistical Simulation

Davy Genbrugge, Lieven Eeckhout
2009 IEEE transactions on computers  
This paper studies statistical simulation as a fast simulation technique for chip multiprocessor (CMP) design space exploration.  ...  Developing fast chip multiprocessor simulation techniques is a challenging problem.  ...  CONCLUSION AND FUTURE WORK Simulating chip multiprocessors is extremely time-consuming.  ... 
doi:10.1109/tc.2009.77 fatcat:be3ssorn4ngb5ly5bugz2ye7n4

Adaptive Thread Scheduling in Chip Multiprocessors

Ismail Akturk, Ozcan Ozturk
2019 International journal of parallel programming  
The full potential of chip multiprocessors remains unexploited due to architecture oblivious thread schedulers employed in operating systems.  ...  We introduce an adaptive cache-hierarchy-aware scheduler that tries to schedule threads in a way that interthread contention is minimized.  ...  [23] focused on L2 cache contention on dual-core chip multiprocessors. They proposed analytical model to predict number of L2 cache misses due to contention of threads on L2 cache. Cazorla et al.  ... 
doi:10.1007/s10766-019-00637-y fatcat:wwtdfzud2rdelpxt3mcipoajxu

Characterizing soft error vulnerability of cache coherence protocols for chip-multiprocessors

Chuanlei Zheng, Shuai Wang
2014 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)  
In this work, we propose to characterize the soft error vulnerability of the L1 data cache in chip-multiprocessors (CMPs) under the influence of different cache coherence protocols.  ...  Recent research has focused on the characterization and optimization for the reliability of data caches in single-core processors.  ...  caches in chip-multiprocessors (CMPs) for different cache coherence protocols.  ... 
doi:10.1109/dft.2014.6962071 dblp:conf/dft/ZhengW14 fatcat:uywermkluzd4bbqutpdib3kzga
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