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A new direction for computer architecture research

C.E. Kozyrakis, D.A. Patterson
1998 Computer  
These proposals covered a wide architecture space, ranging from out-of-order designs to reconfigurable systems.  ...  BILLION-TRANSISTOR PROCESSORS Computer recently produced a special issue on "Billion-Transistor Architectures." 1 The first three articles discussed problems and trends that will affect future processor  ...  In addition, we thank the following for their useful feedback, comments, and criticism on earlier drafts, as well as the grades for vector IRAM: Anant Agarwal  ... 
doi:10.1109/2.730733 fatcat:ykv5f53p5rfdfo4a72a4i25g2q

2019 Index IEEE Computer Architecture Letters Vol. 18

2020 IEEE computer architecture letters  
-June 2019 55-58 Cache storage Code Layout Optimization for Near-Ideal Instruction Cache.  ...  Yasin, A., +, LCA July-Dec. 2019 91-94 Memory architecture A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing.  ...  Quantum computing Quantum Circuits for Dynamic Runtime Assertions in Quantum Computation. Zhou  ... 
doi:10.1109/lca.2020.2964168 fatcat:pv44gn35vrb75jabsid7x62xpm

The Sandbridge SB3011 Platform

John Glossner, Daniel Iancu, Mayan Moudgill, Gary Nacer, Sanjay Jinturkar, Stuart Stanley, Michael Schulte
2007 EURASIP Journal on Embedded Systems  
We provide results for a number of interesting communications and multimedia systems including UMTS, DVB-H, WiMAX, WiFi, and NTSC video decoding.  ...  Each processor core achieves 600 MHz at 0.9 V operation while typically dissipating 75 mW in 90 nm technology. The entire chip typically dissipates less than 500 mW at 0.9 V.  ...  Caches An instruction cache unit (ICU) stores instructions to be fetched for each thread unit. A cache memory works on the principle of locality.  ... 
doi:10.1186/1687-3963-2007-056467 fatcat:uuo67bgefzetpdlm6246mkjdja

The Sandbridge SB3011 Platform

John Glossner, Daniel Iancu, Mayan Moudgill, Gary Nacer, Sanjay Jinturkar, Stuart Stanley, Michael Schulte
2007 EURASIP Journal on Embedded Systems  
We provide results for a number of interesting communications and multimedia systems including UMTS, DVB-H, WiMAX, WiFi, and NTSC video decoding.  ...  Each processor core achieves 600 MHz at 0.9 V operation while typically dissipating 75 mW in 90 nm technology. The entire chip typically dissipates less than 500 mW at 0.9 V.  ...  Caches An instruction cache unit (ICU) stores instructions to be fetched for each thread unit. A cache memory works on the principle of locality.  ... 
doi:10.1155/2007/56467 fatcat:gicryhrnojgjngvd35vfkmhrhe

Polymorphic architectures

Georgi Kuzmanov
2009 Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing - CompSysTech '09  
The base architecture presented is the Molen polymorphic processor -a synergism between a general purpose processor (GPP) and a reconfigurable accelerator.  ...  The author presents some experimental results obtained for a typical supercomputing kernel, matrix multiplication, implemented as a Molen reconfigurable accelerator.  ...  ACKNOWLEDGMENTS To the memory of prof. Stamatis Vassiliadis who unfortunately deceased in 2007 leaving a huge emptiness in the scientific society of the computer architects.  ... 
doi:10.1145/1731740.1731745 dblp:conf/compsystech/Kuzmanov09 fatcat:otowy7tktray3gpbubpa7ztqcu

Chip Multi-Processor Generator

Alex Solomatnikov, Amin Firoozshahian, Wajahat Qadeer, Ofer Shacham, Kyle Kelley, Zain Asgar, Megan Wachs, Rehan Hameed, Mark Horowitz
2007 Proceedings - Design Automation Conference  
The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, universal computing platform  ...  Then, the system "compiles" the program and configuration, tailoring the original framework to create a chip that is optimized toward the desired set of applications.  ...  We have already mapped conventional multithreaded models with shared memory and cache coherence, streaming [10] and transactional memory [11] on this platform.  ... 
doi:10.1109/dac.2007.375164 fatcat:hb7w66ts3na6jmnlntgpsw2vgq

Author Index

2008 2008 IEEE International Symposium on Parallel and Distributed Processing  
A Neocortex Model Implementation on Reconfigurable Logic with Streaming Memory Wadsworth, Daniel M.  ...  Maximal Strips Data Structure to Represent Free Space on Partially Reconfigurable FPGAs Trahay, François A Multithreaded Communication Engine for Multicore Architectures Tran, Duc A.  ... 
doi:10.1109/ipdps.2008.4536576 fatcat:7unikf5ywjhjtdd6xtrmcom3gq

Superspeculative microarchitecture for beyond AD 2000

M.H. Lipasti, J.P. Shen
1997 Computer  
Researchers have proposed reconfigurable computers that employ large arrays of highly programmable build-Employing a broad spectrum of superspeculative techniques can achieve significant performance increases  ...  The experimental, superspeculative microarchitecture Superflow has a potential performance of 9.0 instructions per cycle and realizable performance of 7.3 IPC for the SPEC95 integer suite, without requiring  ...  Furthermore, without a significant multithreaded-application base there may not be a mainstream demand for single-chip SMT processor and CMP implementations.  ... 
doi:10.1109/2.612250 fatcat:ezukhsogtvcnjfga5hqpj5jcsi

A survey of media processing approaches

A. Dasu, S. Panchanathan
2002 IEEE transactions on circuits and systems for video technology (Print)  
The varying processing requirements in multimedia computing for reconfigurable multimedia processing.  ...  A number of implementation strategies have been proposed for processing multimedia data.  ...  In order for vertical multithreading to be effective, the load time from the memory to the cache (upon cache miss) should be much greater than the switch time between instruction streams.  ... 
doi:10.1109/tcsvt.2002.800866 fatcat:2sgvuepvozda5k7jj67em6zeoq

Design principles for a virtual multiprocessor

Philip Machanick
2007 Proceedings of the 2007 annual research conference of the South African institute of computer scientists and information technologists on IT research in developing countries - SAICSIT '07  
This paper explores a model for achieving both in the same design, by reconfiguring functional units on the fly.  ...  A multitasking or multithreaded workload will do better on a CMP design; a floating-point application without many decision points will do better on a machine with ILP as its main parallelism.  ...  to the L1 problem would be to have a separate L1 cache for the clustered case, and individual L1 caches for each core in the CMP case.  ... 
doi:10.1145/1292491.1292500 dblp:conf/saicsit/Machanick07 fatcat:gikire7575cxvboedrlhmmgwgm

Multithreaded virtual-memory-enabled reconfigurable hardware accelerators

Miljan Vuletic, Paolo Ienne, Christopher Claus, Walter Stechele
2006 2006 IEEE International Conference on Field Programmable Technology  
memory for multithreaded hardware accelerators.  ...  In this paper, we introduce a system layer (an OS extension relying on a system hardware extension) that provides: (1) unified virtual memory, (2) platform-agnostic interfacing, and (3) multithreaded execution  ...  ., processors, memories, storage devices, I/O peripherals). There is no such support for user hardware.  ... 
doi:10.1109/fpt.2006.270312 dblp:conf/fpt/VuleticICS06 fatcat:twl3d6d7gvaztexhki6arxvxgi

Scalable Parallel Distributed Coprocessor System for Graph Searching Problems with Massive Data

Wanrong Huang, Xiaodong Yi, Yichun Sun, Yingwen Liu, Shuai Ye, Hengzhu Liu
2017 Scientific Programming  
The core is multithread for streaming processing. And the communication network InfiniBand is adopted for scalability.  ...  A variety of scientific programming methods have been proposed for accelerating and parallelizing BFS because of the poor temporal and spatial locality caused by inherent irregular memory access patterns  ...  The coprocessor is a development board with FPGA (Virtex-7), which is a reconfigurable processor for solving graph problems.  ... 
doi:10.1155/2017/1496104 fatcat:zdtoc6ythndvrkibjkrawq54nq

Reconciling performance and programmability in networking systems

Jayaram Mudigonda, Harrick M. Vin, Stephen W. Keckler
2007 Proceedings of the 2007 conference on Applications, technologies, architectures, and protocols for computer communications - SIGCOMM '07  
To address this challenge, we first make a case for, and then develop a malleable processor architecture that facilitates the dynamic reconfiguration of cache capacity and number of threads to best-suit  ...  Today's commercial processors support two architectural mechanisms-namely, hardware multithreading and caching-to overcome the memory bottleneck.  ...  Louis, for his comments on an earlier draft of this paper.  ... 
doi:10.1145/1282380.1282390 dblp:conf/sigcomm/MudigondaVK07 fatcat:bfyy3kqk2jc2de57fx3o5syyzu

Reconciling performance and programmability in networking systems

Jayaram Mudigonda, Harrick M. Vin, Stephen W. Keckler
2007 Computer communication review  
To address this challenge, we first make a case for, and then develop a malleable processor architecture that facilitates the dynamic reconfiguration of cache capacity and number of threads to best-suit  ...  Today's commercial processors support two architectural mechanisms-namely, hardware multithreading and caching-to overcome the memory bottleneck.  ...  Louis, for his comments on an earlier draft of this paper.  ... 
doi:10.1145/1282427.1282390 fatcat:mz3vyt4ljrfa3pc32w5rrsltd4

Analytical models of Energy and Throughput for Caches in MPSoCs [article]

Arsalan Shahid, Muhammad Tayyab, Muhammad Yasir Qadri, Nadia N. Qadri,, Jameel Ahmed
2019 arXiv   pre-print
With an ever-increasing number of cores on a chip, the role of cache memory has become pivotal.  ...  General trends in computer architecture are shifting more towards parallelism. Multicore architectures have proven to be a major step in processor evolution.  ...  This scheme can be used for systems that support dynamic reconfiguration of memory system to make an early decision on cache sizing for a particular application in execution.  ... 
arXiv:1910.08666v1 fatcat:rxosdhfzkbhhhf3urirgaz4azi
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