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Towards Parallel Boolean Functional Synthesis [article]

S. Akshay, Supratik Chakraborty, Ajith K. John, Shetal Shah
2017 arXiv   pre-print
This is called the Boolean functional synthesis problem and has applications in several areas.  ...  In this paper, we present the first parallel approach for solving this problem, using compositional and CEGAR-style reasoning as key building blocks.  ...  In this paper, we present, to the best of our knowledge, the first parallel algorithm for Boolean functional synthesis.  ... 
arXiv:1703.01440v1 fatcat:x7zlnmovrvhbxmcrllwkpj2ahi

AUTOMATING TECHNOLOGY ADAPTATION IN DESIGN SYNTHESIS [chapter]

JAMES R. KIPPS, DANIEL D. GAJSKI
1991 Applications of Learning and Planning Methods  
Existing logic synthesis tools are largely restricted to designing combina tional circuits described by Boolean equations.  ...  Existing tools are also restricted to implementing designs with a small set of widely available physical cells, such as one-and two-level Boolean gates.  ...  Designing by Function Human designers overcome the problems that limit current approaches to logic synthesis by viewing components as functions, rather than as sets of Boolean equations.  ... 
doi:10.1142/9789812812414_0006 fatcat:audctk4uxbflvormes7lldjoru

Reversible Logic Circuit Complexity Analysis via Functional Decomposition [article]

Anupam Chattopadhyay, Anubhab Baksi
2016 arXiv   pre-print
In this paper, we connect this problem with the multiplicative complexity analysis of classical Boolean functions.  ...  The ancilla-free synthesis methods by using transformations and by starting from an Exclusive Sum-of-Product (ESOP) formulation remain, theoretically, the synthesis methods for achieving least gate count  ...  Multiplicative Complexity In parallel with the efforts for enumerating the reversible circuit complexity, progress in the analysis of classical Boolean functions in terms of multiplicative complexity is  ... 
arXiv:1602.00101v2 fatcat:rmcglcpgmbhkpeblqflqbth7wq

A Case Study on Controller Synthesis for Data-Intensive Embedded Systems

Abdoulaye Gamatié, Huafeng Yu, Gwenaël Delaval, Éric Rutten
2009 2009 International Conference on Embedded Software and Systems  
) with Boolean functions of states and inputs (f : B n → N).  ...  We particularly address the synthesis of a safe application controller enforcing correct behaviors w.r.t. functional and non functional requirements.  ... 
doi:10.1109/icess.2009.12 dblp:conf/icess/GamatieYDR09 fatcat:6ipraialmzgtthzntc6pzxzhii

Synthesis of threshold logic circuits using tree matching

Tejaswi Gowda, Samuel Leshner, Sarma Vrudhula, Goran Konjevod
2007 2007 18th European Conference on Circuit Theory and Design  
Threshold logic has been known to be an alternative to Boolean logic for over four decades now.  ...  We present a novel synthesis algorithm for threshold circuits based on tree matching.  ...  We believe that this is an important step towards development of TL design automation methods that are independent of Boolean logic optimization. II.  ... 
doi:10.1109/ecctd.2007.4529730 dblp:conf/ecctd/GowdaLVK07 fatcat:t2hnadoykjetnpkdoq4yis4cda

A XOR Threshold Logic Implementation Through Resonant Tunneling Diode

Nitesh Kumar Dixit
2012 International Journal of VLSI Design & Communication Systems  
Resonant tunneling diodes (RTDs) have functional versatility and high speed switching capability. The integration of resonant tunneling diodes and MOS transistor makes threshold gates and logics.  ...  The XOR function is realized by placing a series connected MOSFET pair in parallel with the driver RTD.  ...  While important steps have been made towards the hardware implementation of TL computing units the TL utilization in Very Large Scale Integration (VLSI) also requires the existence of high-level TL synthesis  ... 
doi:10.5121/vlsic.2012.3511 fatcat:vmtqoiavqjcyflktzmwxakosbm

Synthesis of Parallel Synchronous Software

Pantea Kiaei, Patrick Schaumont
2020 IEEE Embedded Systems Letters  
Using logic synthesis and code generation, we derive a parallel synchronous implementation of this design.  ...  We describe a parallel synchronous software model, which executes as N parallel threads on a processor with word-length N.  ...  SYNTHESIS OF PARALLEL SYNCHRONOUS SOFTWARE We next demonstrate how to create PSP.  ... 
doi:10.1109/les.2020.2992051 fatcat:mtckpmakz5hmnjfebaozw3muae

Discrete Controller Synthesis for Infinite State Systems with ReaX

Nicolas Berthier, Hervé Marchand
2014 IFAC Proceedings Volumes  
Fig. 4 .Fig. 5 . 45 Synthesis times for the parallel tasks example. (Sigali takes more than 56h if n = 51.)  ...  Performance Results We report in Figure 6 the whole execution times (synthesis, plus triangulation of the controller in case of success) for each series of experiments, and various numbers of parallel  ... 
doi:10.3182/20140514-3-fr-4046.00099 fatcat:tlglt7lngvhipcmkj6bogtctpi

Division-Based Versus General Decomposition- Based Multiple-Level Logic Synthesis

Frank Volf, Lech Jóźwiak, Mario Stevens
1995 VLSI design (Print)  
During the last decade, many different approaches have been proposed to solve the multiple-level synthesis problem with different minimum functionally complete systems of primitive logic blocks.  ...  The traditional methods are therefore not suitable for synthesis with many modem building blocks.  ...  mapp ing must again perform synthesis using the previously synthesised network as only a functional specification Using decomposition-based synthesis this problem does not exist: the synthesis process  ... 
doi:10.1155/1995/19823 fatcat:srce5n74wvf4lcy34y7njsfgsy

Optimising attractor computation in Boolean automata networks [article]

Kévin Perrot, Pacôme Perrotin, Sylvain Sené
2020 arXiv   pre-print
This paper details a method for optimising the size of Boolean automata networks in order to compute their attractors under the parallel update schedule.  ...  distinct from parallel.  ...  allow together towards the computation of BAN dynamics.  ... 
arXiv:2005.14531v2 fatcat:vpgnow66tndfpbigqm2pkspcf4

Synthesis of parallel adders from if-decision diagrams

A. A. Prihozhy
2020 Sistemnyj Analiz i Prikladnaâ Informatika  
If-decision diagrams provide a parallel many-bit adder model with the time complexity of Ο(log2n) and area complexity of Ο(n×log2n).  ...  FPGA-based synthesis results and case-study comparisons of the if-diagram-based adders to the Brent-Kung and majority-invertor gate adders show that the new adder architecture leads to faster and smaller  ...  We call function f(x) = ϕ on (x) a value function, and call function d(x) = ¬ϕ dc (x) a domain function where ¬ is Boolean inversion.  ... 
doi:10.21122/2309-4923-2020-2-61-70 fatcat:c5apneo23zc3dbi3uwaw7x5qsm

Boolean Evaluation with a Pairing and Unpairing Function

Paul Tarau, Brenda Luderman
2012 2012 14th International Symposium on Symbolic and Numeric Algorithms for Scientific Computing  
A pairing function is a bijection f : N × N → N. Its inverse is called an unpairing function.  ...  We show that boolean logic on bitvector variables can be expressed as compositions of pairing/unpairing operations which can emulate boolean evaluation of ordered binary decision trees (OBDTs) of a canonical  ...  The somewhat surprising connection with boolean evaluation hints towards applications to the theory of of boolean functions as well as boolean circuit complexity and circuit synthesis.  ... 
doi:10.1109/synasc.2012.20 dblp:conf/synasc/TarauL12 fatcat:plueq6fyvna7lfpp52nxaztenu

Formal Verification of Hardware Components in Critical Systems

Wilayat Khan, Muhammad Kamran, Syed Rameez Naqvi, Farrukh Aslam Khan, Ahmed S. Alghamdi, Eesa Alsolami
2020 Wireless Communications and Mobile Computing  
Boolean functions.  ...  define the algebraic manipulation (step-by-step procedure of proving functional equivalence of functions) used in Boolean function simplification, and (3) verify functional correctness and reliability  ...  While their work is more focused towards synthesis based on Coq's code extraction feature, our work embeds Boolean algebra as a gate-level description language for circuit's description.  ... 
doi:10.1155/2020/7346763 fatcat:nwrynuotc5h3zarf5iuri7l4si

High-Level Graphical Abstraction in Digital Design

Murray W. Pearson, Paul J. Lyons, Mark D. Apperley
1996 VLSI design (Print)  
representing abstract architectures; text is better for functionality.The designer should not have to translate graphical information into text.Graphical and textual design capture can be integrated with synthesis  ...  sequentially or in parallel.  ...  It also synthesises the data channels, via which the functional units communicate, and associated synchronisation hardware.  ... 
doi:10.1155/1996/69892 fatcat:nsl5lgc4mbb4pjvih5q4t6nzju

AEON: Attractor Bifurcation Analysis of Parametrised Boolean Networks [chapter]

Nikola Beneš, Luboš Brim, Jakub Kadlecaj, Samuel Pastva, David Šafránek
2020 Lecture Notes in Computer Science  
To fight the state-space and parameter-space explosion problem the tool uses a parallel semi-symbolic algorithm.  ...  We present a tool for analysing bifurcations in asynchronous parametrised Boolean networks.  ...  The development of formal methods for analysis and synthesis of Boolean networks has recently attracted a lot of attention [11, 18, 20, 28, 36] .  ... 
doi:10.1007/978-3-030-53288-8_28 fatcat:lygd47u6gfbolj4mq6x3k2bvla
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