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Distributed shared memory: concepts and systems

J. Protic, M. Tomasevic, V. Milutinovic
1996 IEEE Parallel & Distributed Technology Systems & Applications  
She is currently working toward her PhD in the field of DSM. Her research interests are in computer architecture, distributed systems, and performance analysis.  ...  His research interests are computer architectures, multiprocessor systems, and distributed shared-memory systems. He can be reached a t etomasev@ubbg.etf.bg.ac.yu.  ...  In addition, the scalability and cost-effectiveness of underlymg dismbuted-memory systems are also inherited.  ... 
doi:10.1109/88.494605 fatcat:56jusk7vobepvhcvroadujiiae

Enhancing the performance of autoscheduling in Distributed Shared Memory multiprocessors [chapter]

Dimitrios S. Nikolopoulos, Eleftherios D. Polychronopoulos, Theodore S. Papatheodorou
1998 Lecture Notes in Computer Science  
This paper presents a technique that enhances the performance of autoscheduling in Distributed Shared Memory (DSM) multiprocessors, targetting mainly at medium and large scale systems, where poor data  ...  Our technique partitions the application Hierarchical Task Graph and maps the derived partitions to clusters of processors in the DSM architecture.  ...  The development of programming models and compilation techniques that exploit the advantages and overcome the architectural bottlenecks of DSM systems remains a challenge.  ... 
doi:10.1007/bfb0057892 fatcat:sdudtgqxeje3jhwt56fxhzipwq

SMiLE: an integrated, multi-paradigm software infrastructure for SCI-based clusters

Martin Schulz, Jie Tao, Carsten Trinitis, Wolfgang Karl
2003 Future generations computer systems  
Shared Memory in a LAN-like Environment (SMiLE) provides such an infrastructure for SCI (Scalable Coherent Interface) based clusters.  ...  It includes support for a large range of message passing libraries as well as for almost arbitrary shared memory programming models.  ...  This architecture therefore provides a good tradeoff between cost effectiveness and high performance communication support.  ... 
doi:10.1016/s0167-739x(03)00032-3 fatcat:limhgsf2cve75hyhadzz2mz2hy

The Wisconsin Wind Tunnel project

Mark D. Hill, James R. Larus, David A. Wood
1994 SIGARCH Computer Architecture News  
This document lists contributors to the Wisconsin Wind Tunnel Project, gives a brief description of the project, and presents references and abstracts to its principal papers, including how to obtain them  ...  These speedups indicate that decoupled designs can potentially provide a cost-effective alternative to complex high-end DSM systems.  ...  This paper argues, however, that compiler-implemented shared memory, despite its shortcomings, has the potential to exploit more effectively the resources in a parallel computer.  ... 
doi:10.1145/192537.192543 fatcat:rvtgkgeonnba3cdbociaiglrdq

The AXIOM project (Agile, eXtensible, fast I/O Module)

Dimitris Theodoropoulos, Dionisis Pnevmatikatos, Carlos Alvarez, Eduard Ayguade, Javier Bueno, Antonio Filgueras, Daniel Jimenez-Gonzalez, Xavier Martorell, Nacho Navarro, Carlos Segura, Carles Fernandez, David Oro (+4 others)
2015 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)  
We will work to provide an integrated environment that supports programmability of the parallel, interconnected nodes that form a CPS system, and evaluate our ideas using demanding test application scenarios  ...  at best existing standards at minimal costs.  ...  Finally, we believe that AXIOM addresses the ultimate need for integrating in the competent and motivated organizations from all over Europe able to contribute with new research ideas and to lead competitive  ... 
doi:10.1109/samos.2015.7363684 dblp:conf/samos/TheodoropoulosP15 fatcat:rhj5wzl6rzdwdn7nzbfk22sls4

Trends of terascale computing Chips in the next ten years

Zhonghai Lu, Axel Jantsch
2009 2009 IEEE 8th International Conference on ASIC  
Four foreseeable trends are: from single core to many cores, from bus-based to network-based interconnect, from centralized memory to distributed memory, and from 2D integration to 3D integration.  ...  Moore's law steadily continues though facing a number of challenges.  ...  From Centralized Memory to Distributed Memory Memory is a first class citizen in a computing system. Its organization and size are crucial for performance, power and cost.  ... 
doi:10.1109/asicon.2009.5351607 fatcat:eebrdqmqkzf35jakxtbg4eyyle

Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips

Xiaowen Chen
2015 Journal of Software  
The SMTp [16] exploits SMT in conjunction with a standard integrated memory controller to enable a coherence protocol thread used to support DSM multiprocessors.  ...  Furthermore, the MAGIC and the NP organize memory banks to form a cache-coherent shared memory.  ...  Note that a node can also be a memory node without a processor.  ... 
doi:10.17706/jsw.10.2.142-161 fatcat:jovscxriofb5hfi7brsnphkiqe

SMTp

Mainak Chaudhuri, Mark Heinrich
2004 SIGARCH Computer Architecture News  
We introduce the SMTp architecture-an SMT processor augmented with a coherence protocol thread context, that together with a standard integrated memory controller can enable the design of (among other  ...  We then compare SMTp performance to that of various conventional DSM machines with normal SMT processors both with and without integrated memory controllers.  ...  With the trend toward integrated memory controllers, one can ask how do you design the next-generation scalable DSM machine?  ... 
doi:10.1145/1028176.1006712 fatcat:sjoldsrcefeg5gpqc2f475eh6a

Popcorn

Antonio Barbalace, Marina Sadini, Saif Ansary, Christopher Jelesnianski, Akshay Ravichandran, Cagil Kendir, Alastair Murray, Binoy Ravindran
2015 Proceedings of the Tenth European Conference on Computer Systems - EuroSys '15  
The recent possibility of integrating multiple-OS-capable, high-core-count, heterogeneous-ISA processors in the same platform poses a question: given the tight integration between system components, can  ...  Applications run transparently amongst different ISA processors while exploiting the most optimized instruction set for each code block.  ...  platforms, such as platforms that integrate Tilera TileGx [32] and x86, or ARM and x86.  ... 
doi:10.1145/2741948.2741962 dblp:conf/eurosys/BarbalaceSAJRKM15 fatcat:o6ibsell2rc2rkxei7vumqyeti

Missing the memory wall

Ashley Saulsbury, Fong Pong, Andreas Nowatzyk
1996 SIGARCH Computer Architecture News  
This paper argues for an integrated system approach that uses less-powerful CPUs that are tightly integrated with advanced memory technologies to build competitive systems with greatly reduced cost and  ...  Based on a design study using the next generation 0.25µm, 256Mbit dynamic random-access memory (DRAM) process and on the analysis of existing machines, we show that processor memory integration can be  ...  feedback and inspiration they received from Gunes Aybay, Clement Fang, Howard Davidson, Mark Hill, Sally McKee, William Radke, Eugen Schenfeld, Sanjay Vishin, the engineers of the Sparc Technology Business organization  ... 
doi:10.1145/232974.232984 fatcat:w5c3hi3725dpdpc76725f5pyqq

Missing the memory wall

Ashley Saulsbury, Fong Pong, Andreas Nowatzyk
1996 Proceedings of the 23rd annual international symposium on Computer architecture - ISCA '96  
This paper argues for an integrated system approach that uses less-powerful CPUs that are tightly integrated with advanced memory technologies to build competitive systems with greatly reduced cost and  ...  Based on a design study using the next generation 0.25µm, 256Mbit dynamic random-access memory (DRAM) process and on the analysis of existing machines, we show that processor memory integration can be  ...  feedback and inspiration they received from Gunes Aybay, Clement Fang, Howard Davidson, Mark Hill, Sally McKee, William Radke, Eugen Schenfeld, Sanjay Vishin, the engineers of the Sparc Technology Business organization  ... 
doi:10.1145/232973.232984 dblp:conf/isca/SaulsburyPN96 fatcat:ut72ah2zxzh73onrac3vems5aq

A Case for Dynamic Page Migration in Multiple-Writer Software DSM Systems

Thomas Repantis, Christos D. Antonopoulos, Vana Kalogeraki, Theodore S. Papatheodorou
2005 Proceedings IEEE International Conference on Cluster Computing  
In these systems each page has a designated home node; yet our protocol allows a node that heavily modifies a page to become its new home. The new protocol targets multiplewriter DSMs, i.e.  ...  In this paper we introduce a protocol for dynamically migrating memory pages in home-based SDSM systems.  ...  A Software DSM (SDSM) layer may be offered as either part of the operating system kernel or as a run-time library. The programming simplicity that SDSMs offer does however come at a performance cost.  ... 
doi:10.1109/clustr.2005.347077 dblp:conf/cluster/RepantisAKP05 fatcat:ygyb5hneqjbhpn6twsgrggs7h4

Emerging Database Systems in Support of Scientific Data [chapter]

Per Svensson, Peter Boncz, Milena Ivanova, Martin Kersten, Niels Nes, Doron Rotem
2009 Scientific Data Management  
This chapter surveys and discusses the evolution of a certain class of database architectures, more recently referred to as "vertical databases".  ...  Next, the chapter covers in detail the architecture and design considerations of a particular (open source) vertical database system, called MonetDB.  ...  In this case, allowing array lookup as a way to locate tuples in an entire table, in effect means that MonetDB exploits the MMU (memory management unit) hardware in a CPU to offer a very-fast O(1) lookup  ... 
doi:10.1201/9781420069815-c7 fatcat:ft3mckhzr5agfhopo6awmhwk7e

Scheduler-Activated Dynamic Page Migration for Multiprogrammed DSM Multiprocessors

Dimitrios S. Nikolopoulos, Constantine D. Polychronopoulos, Theodore S. Papatheodorou, Jesús Labarta, Eduard Ayguadé
2002 Journal of Parallel and Distributed Computing  
On cachecoherent distributed shared-memory (DSM) multiprocessors, such scheduler interventions tend to increase the rate of remote memory accesses.  ...  The purpose of the algorithm is the early detection of pages that will most likely be accessed remotely by threads associated with them via a thread-to-memory affinity relation.  ...  The commercial success of these systems is a synergy of three factors: scalability, which is enabled by the DSM architecture; cost effectiveness, which is enabled by the use of off-the-shelf building components  ... 
doi:10.1006/jpdc.2001.1817 fatcat:mm4g6niwc5e4dn4adqub77grbu

Towards Virtual Shared Memory for Non-cache-coherent Multicore Systems

Bharath Ramesh, Calvin J. Ribbens, Srinidhi Varadarajan
2013 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum  
We discuss how our recently proposed DSM system and its memory consistency model maps to the heterogeneous node context, and present experimental results that highlight the advantages and challenges of  ...  This paper examines the potential of distributed shared memory (DSM) for addressing this programming challenge.  ...  If a cache becomes full the eviction policy used is biased towards pages that have been written to.  ... 
doi:10.1109/ipdpsw.2013.73 dblp:conf/ipps/RameshRV13 fatcat:oaokbx7kjrb3hpyuuia7vur6hu
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