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Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches

Minje Jun, Sungjoo Yoo, Eui-Young Chung
2008 2008 Asia and South Pacific Design Automation Conference  
The optimal topology consists of multiple crossbar switches and some of them can be connected in a cascaded fashion for higher clock frequency and/or area efficiency.  ...  We present a topology synthesis method for high performance System-on-Chip (SoC) design.  ...  Yoo et al. proposed a topology synthesis method using crossbar switches in a cascaded fashion based on simulated annealing [19] .  ... 
doi:10.1109/aspdac.2008.4484019 dblp:conf/aspdac/JunYC08 fatcat:4rd6ifkzxjaczmqpfgycxdyo4a

Design of On-Chip Crossbar Network Topology Using Chained Edge Partitioning

M. Jun, E.-Y. Chung
2010 Computer journal  
This paper proposes an efficient topology synthesis method for on-chip interconnection network based on crossbar switches.  ...  Recently, several works proposed a cascaded crossbar switch architecture and the corresponding topology synthesis methods in [6] [7] [8] .  ...  In our formulation, we consider a cascaded crossbar switch architecture which is irregular from the topological point of view.  ... 
doi:10.1093/comjnl/bxq020 fatcat:6ogxzeviknaobi5l55y2zeg7gu

Interconnect synthesis of heterogeneous accelerators in a shared memory architecture

Yu-Ting Chen, Jason Cong
2015 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)  
The experimental results show that we can reduce more than 45% of the switches of the partial crossbar compared to the best known method.  ...  We first provide an optimal layer of partial crossbar that connects the heterogeneous accelerators and shared memory banks with a minimum number of switches.  ...  The topology synthesis in this layer has not been considered together with a given partial crossbar topology from the existing work. III.  ... 
doi:10.1109/islped.2015.7273540 dblp:conf/islped/ChenC15 fatcat:cnjlygfbtzeihg34ldmeyskmqm

Network-on-Chip Design [chapter]

Haseeb Bokhari, Sri Parameswaran
2017 Handbook of Hardware/Software Codesign  
This is followed by a discussion on the commonly used power-saving techniques used for NoCs and the drawbacks and limitations of these techniques.  ...  Packet-switched network on chip (NoC) is envisioned as a scalable and cost-effective communication fabric for multi-core architectures with tens and hundreds of cores.  ...  [72] proposed a complete design method for application-specific crossbar synthesis.  ... 
doi:10.1007/978-94-017-7267-9_16 fatcat:2rttwll4qvfq7jnvuc3moocy5e

MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices

Paul Somnath, Swarup Bhunia
2008 2008 Asia and South Pacific Design Automation Conference  
level restoration and cascading logic blocks); 3) existing techniques for defect tolerance in memory array can be easily extended to this framework.  ...  While the emerging nanoscale devices show promises in terms of integration density and computing power, system design with these devices involve some major challenges, such as bottom-up design approach  ...  Although most of these emerging nanodevices are still in their infancy, they hold tremendous potential in terms of integration density (~10 10 devices/cm 2 ), low power operation and higher switching speed  ... 
doi:10.1109/aspdac.2008.4484057 dblp:conf/aspdac/SomnathB08 fatcat:45msu76ycrfrdovuhdfpzi35pm

Adapting the RACER Architecture to Integrate Improved In-ReRAM Logic Primitives

Minh S. Q. Truong, Liting Shen, Alexander Glass, Alison Hoffmann, L. Richard Carley, James A. Bain, Saugata Ghose
2022 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
to support a wide range of logic families, (2) evaluating three logic families proposed by prior work, and (3) proposing and evaluating a new logic family called OSCAR that significantly relaxes the switching  ...  Area & Circuit Synthesis Analysis Table I shows a breakdown of the area, static power, and dynamic power consumed by each component of the RACER circuitry.  ...  CASCADE using low-latency, highenergy MAC instructions Overall, we find that our new high-performance MAC instruction allows RACER to outperform CASCADE for many, but not all, microbenchmarks.  ... 
doi:10.1109/jetcas.2022.3171765 fatcat:nxxqef6uwzhr3imo5bpnnljlgq

A Scalable Memory-Based Reconfigurable Computing Framework for Nanoscale Crossbar

Somnath Paul, Swarup Bhunia
2012 IEEE transactions on nanotechnology  
To address some of the design challenges in molecular crossbar, we propose "MBARC", where memory, instead of switch based logic functions, is used as the computing element.  ...  MBARC leverages on the fact that regular and periodic structures of molecular crossbar are attractive for dense memory design.  ...  Rotaxane molecules sandwiched between the Ti/Pt nanowires at each molecular crossbar junction can be switched from a state of high resistance to a state of low resistance and vice versa on the application  ... 
doi:10.1109/tnano.2010.2041556 fatcat:lpgg7aro4ndypjsn5fmf5y3hgm

Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks

Johnnie Chan, Gilbert Hendry, Keren Bergman, Luca P. Carloni
2011 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Recent progress in silicon photonics research has enabled the demonstration of all the necessary optical building blocks for creating extremely highbandwidth density and energy-efficient links for on-chip  ...  In this paper, we present a methodology for characterizing and modeling fundamental photonic building blocks which can subsequently be combined to form full photonic network architectures.  ...  Since many topologies require a large number of waveguide crossings, it is important for these devices to exhibit both low insertion loss and low crosstalk.  ... 
doi:10.1109/tcad.2011.2157157 fatcat:rmaazvpdkfhmxo4k3uenh6vk5u

Implementation of Dynamic and Efficient Virtual Channel Router for Network on Chip with Virtual Channel Arbitration Reduction and Parallel Switch Allocation Unit

Minakshi M. Wanjari, Electronics and Telecommunication Engineering Department, G. H. Raisoni College of Engineering, Nagpur, India, Pankaj Agrawal, Ravindra V. Kshirsagar
2022 International Journal of Emerging Technology and Advanced Engineering  
result in minimizing the latency, area and power.  ...  Keywords—Intellectual Property (IP), Network on Chip (NoC), Network Interface (NI), Switch allocation (SA), System-on-Chip (SoC), Virtual channel (VC), Virtual channel arbitration (VA)  ...  , and (d) the XBAR switch which is a Crossbar.  ... 
doi:10.46338/ijetae022_19 fatcat:xssfa5gu4rdqvcn637i7r3v5v4

Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support

Sonda CHTOUROU, Zied MARRAKCHI, Emna AMOURI, Vinod PANGRACIOUS, Mohamed ABID, Habib MEHREZ
2017 Turkish Journal of Electrical Engineering and Computer Sciences  
The exploration results showed that architecture with high cluster size provides high speed performance and low power dissipation.  ...  Field programmable gate arrays (FPGAs) have become an attractive implementation medium for digital circuits.  ...  For example, improving the logic synthesis algorithm step can decrease the amount and depth of needed logic and power dissipation [3] .  ... 
doi:10.3906/elk-1506-51 fatcat:2obvd25n4jhxvetdtpfwnrhw6i

Towards compelling cases for the viability of silicon-nanophotonic technology in future manycore systems

Luca Ramini, Herve Tatenguem Fankem, Alberto Ghiribaldi, Paolo Grani, Marta Ortin-Obon, Anja Boos, Sandro Bartolini
2014 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS)  
The quality metrics of this latter are derived from synthesis and place&route on an industrial 40nm low-power technology library.  ...  Moreover, real synthesis runs of the target ENoC on a 40nm industrial low-power technology will provide the reference quality metrics the competing optical NoC solutions are contrasted with.  ... 
doi:10.1109/nocs.2014.7008778 dblp:conf/nocs/RaminiFGGOBB14 fatcat:rfhirddgcrflld2hjkb24ajzti

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

Yaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang, Weichen Liu, Mahdi Nikdast
2012 ACM Journal on Emerging Technologies in Computing Systems  
Both of the unfolded and folded torus topologies are explored for THOE.  ...  It employs several new techniques including floorplan optimization, an adaptive power control mechanism, low-latency control protocols, and hybrid optical-electrical routers with a low-power optical switching  ...  It employs several new techniques including floorplan optimization, an adaptive power control mechanism, low-latency control protocols, and a new low-power optical switching fabric.  ... 
doi:10.1145/2093145.2093150 fatcat:nvdo2qss4vddjjeshzg4nugxai

Efficient and programmable ethernet switching with a NoC-enhanced FPGA

Andrew Bitar, Jeffrey Cassidy, Natalie Enright Jerger, Vaughn Betz
2014 Proceedings of the tenth ACM/IEEE symposium on Architectures for networking and communications systems - ANCS '14  
We compare a NoC-based 16×16 network switch for 10-Gigabit Ethernet traffic to a recent innovative FPGA-based switch fabric design.  ...  While FPGAs are extensively used for packet parsing, inspection and classification, they have seen less use as the switch fabric between network ports.  ...  areas, and the anonymous reviewers for their valuable feedback.  ... 
doi:10.1145/2658260.2658272 dblp:conf/ancs/BitarCJB14 fatcat:j7qononx2ngqrfdvocuqg6k5ge

Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture

A Strano, C Gómez, D Ludovici, M Favalli, M E Gómez, D Bertozzi
2011 2011 Design, Automation & Test in Europe  
Concurrent BIST operations are carried out after reset at each switch, thus resulting in scalable test application time with network size.  ...  Low fault coverage is achieved for the switch controller, moreover the methodology applies only to a 2D mesh.  ...  routing module is cascaded to the buffer stage of each input port.  ... 
doi:10.1109/date.2011.5763109 dblp:conf/date/StranoGLFGB11 fatcat:ilsnjuwfnjeencfyuui6ef5baa

A study of asynchronous design methodology for robust CMOS-nano hybrid system design

Rajat Subhra Chakraborty, Swarup Bhunia
2009 ACM Journal on Emerging Technologies in Computing Systems  
We then develop the methodology and an automated synthesis flow to support two different asynchronous design approaches (Micropipelines and Four phase Dual-rail) for system designs using nano-crossbar  ...  However, circuit design using molecular switches involve some major challenges: 1) lack of voltage gain of these switches that prevents logic cascading; 2) large output voltage level degradation; 3) vulnerability  ...  An automatic circuit synthesis framework is developed to synthesize circuits from their specifications into the nanoscale crossbar platform (Section 5). (4) We present simulation results for a set of combinational  ... 
doi:10.1145/1568485.1568486 fatcat:cdnngvcxcrfudf2szxltnk3z7q
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