A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2015; you can also visit the original URL.
The file type is application/pdf.
Filters
Automating the design of mLUT MPSoPC FPGAs in the cloud
2012
22nd International Conference on Field Programmable Logic and Applications (FPL)
Preserved Fulltext
Modern platform FPGAs are over the million-LUT level, large enough to support complete heterogeneous Multiprocessor System-On-Chips (MPSoCs). ...
Instead, new automated system assembly approaches will be required to handle these levels of system complexity and diversity. ...
INTRODUCTION Current Platform FPGAs contain more than a million LUTs, a sufficient density to turn a single chip FPGA into a complete multiprocessor system on chip (MPSoC). ...
doi:10.1109/fpl.2012.6339186
dblp:conf/fpl/CartwrightFMSHAA12
fatcat:ab457tma7rb7dan4wmpokry6ae
Emulating Transactional Memory on FPGA Multiprocessors
[chapter]
2011
Lecture Notes in Computer Science
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
We analyze and compare these two architectures to a lock based multiprocessor prototype, discussing the trade-offs in terms of design complexity, performance and scalability. ...
In this paper we discuss the development of two emulation platforms for transactional memory systems on a single Field Programmable Gate Array (FPGA). ...
Several systems supporting transactional memories have been proposed. In [5] , a system based on the ALTERA toolchain is presented. ...
doi:10.1007/978-3-642-19137-4_7
fatcat:6flipy4ij5hqjf2dwbjfxpdmda
A dual-priority real-time multiprocessor system on FPGA for automotive applications
2008
Proceedings of the conference on Design, automation and test in Europe - DATE '08
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
This paper presents the implementation of a dualpriority scheduling algorithm for real-time embedded systems on a shared memory multiprocessor on FPGA. ...
As multiprocessors became the standard for embedded systems, the attention has been focused on proposing scheduling solutions that allow good 1 978-3-9810801-3-1/DATE08 ...
Introduction Multiprocessor Systems-on-Chip (MPSoCs), composed of several processing elements and on-chip memories, have become the standard for implementing embedded systems. ...
doi:10.1145/1403375.1403625
fatcat:gqld4wkxhzalpgxcb4wieiehjy
A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications
2008
2008 Design, Automation and Test in Europe
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
This paper presents the implementation of a dualpriority scheduling algorithm for real-time embedded systems on a shared memory multiprocessor on FPGA. ...
As multiprocessors became the standard for embedded systems, the attention has been focused on proposing scheduling solutions that allow good 1 978-3-9810801-3-1/DATE08 ...
Introduction Multiprocessor Systems-on-Chip (MPSoCs), composed of several processing elements and on-chip memories, have become the standard for implementing embedded systems. ...
doi:10.1109/date.2008.4484818
dblp:conf/date/TumeoBCCMPFS08
fatcat:2qqqxffnyvgnfgsxy2ot5zmx6i
Compiling Scilab to high performance embedded multicore systems
2013
Microprocessors and microsystems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
The mapping process of high performance embedded applications to today's multiprocessor system-onchip devices suffers from a complex toolchain and programming process. ...
a Scilab-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from a high level of abstraction. ...
ways to gain high performance on embedded systems. ...
doi:10.1016/j.micpro.2013.07.004
fatcat:pdh6kpwp25galdrdtvpv45l2cy
Taxim: A Toolchain for Automated and Configurable Simulation for Embedded Multiprocessor Design
[article]
2016
arXiv
pre-print
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
In this paper, we introduce Taxim, a toolchain that can automatically create requested multicore on-chip topologies along with minimizing the simulation time due to repetitive tasks between architectural ...
Multicore embedded systems have been constantly researched to improve the efficiency by changing certain metrics, such as processor, memory, cache hierarchies and their cache configurations. ...
The work in [8] takes a range of high and low-level parameters to improve accuracy in the design of a multiprocessor system on a chip. ...
arXiv:1601.03341v1
fatcat:o7do66uz45abvaawua2rocdsyi
Parallelism and the ARM instruction set architecture
2005
Computer
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
The ARM version of RISC differed in many ways, partly because the ARM processor became an embedded processor designed to be located within a system-on-chip device. 1 Although this kept the main design ...
For thread-level parallelism, ARM needed to improve exception handling to prepare for the increased complexity in handling multithreading on multiple processors. ...
doi:10.1109/mc.2005.239
fatcat:pj5stahpc5amxpn7oixx6k5o2y
Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System
2011
2011 21st International Conference on Field Programmable Logic and Applications
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
We also provide a small MIPS cross-compiler toolchain to assist in developing software for Heracles. ...
In the baseline design, the microprocessor is attached to two caches, one instruction cache and one data cache, which are oblivious to the global memory organization. ...
In [9] Del Valle et al present an FPGA-based emulation framework for multiprocessor system-on-chip (MPSoC) architectures. ...
doi:10.1109/fpl.2011.70
dblp:conf/fpl/KinsyPD11
fatcat:s6x3z553kfcpzbdfq36otatnti
A design kit for a fully working shared memory multiprocessor on FPGA
2007
Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
This idea can be applied both to a scratchpadbased architecture or a cache-based one. ...
This paper presents a framework to design a shared memory multiprocessor on a programmable platform. We propose a complete flow, composed by a programming model and a template architecture. ...
It's important to note that all these components can be easily integrated in the common EDK flow, in order to permit fast prototyping of multiprocessor system-on-chip. ...
doi:10.1145/1228784.1228841
dblp:conf/glvlsi/TumeoMPFS07
fatcat:5jvrar7jnvejli4xwuvkeu567y
libEOMP
2013
Proceedings of the 2013 International Workshop on Programming Models and Applications for Multicores and Manycores - PMAM '13
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
In this paper, we extend the usage of a high-level programming model, OpenMP, to multicore embedded systems. ...
In recent years rapid revolution of Multiprocessor Systemon-Chip (MPSoC) poses new challenges for programming such architectures in an efficient manner. ...
The MRAPI provides essential capabilities required to manage shared resources in embedded systems, including heterogeneous/homogeneous cores on-chips, hardware accelerators and memory regions. ...
doi:10.1145/2442992.2443001
dblp:conf/ppopp/WangCCH13
fatcat:hpivtj2kijb3nfu6zakmzpxjsa
A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip
2009
International Journal of Reconfigurable Computing
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
The developed scheme is validated by a multiprocessor system implemented on reconfigurable hardware as well as by a classification of existing static and reconfigurable processor systems. ...
A classification scheme for computer systems was provided in 1966 by Flynn where single/multiple data and instruction streams were combined to four types of architectures. ...
Nowadays the System-on-Chip approach allows for integration of multiple devices on one chip die. Many difficulties in hardware technology were resolved. ...
doi:10.1155/2009/395018
fatcat:y5j3rgn7ejdojmjq7wfv26bymu
An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration
2006
Proceedings of the Design Automation & Test in Europe Conference
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2007; you can also visit the original URL.
The file type is application/pdf.
In recent years, increasing manufacturing density has allowed the development of Multi-Processor Systems-on-Chip (MPSoCs). ...
We tackle this challenge by proposing an integrated approach where state-of-the-art platform modeling infrastructures, at the IP core level and at the system level, meet to provide the designer with maximum ...
Three layers of memory devices are defined: (1) on-tile, strongly coupled to the processor, e.g. caches and ScratchPad Memories (SPMs); (2) on-chip, attached to the system interconnect; (3) off-chip, driven ...
doi:10.1109/date.2006.244000
dblp:conf/date/AngioliniCLFFB06
fatcat:kjfkgmhbyfcgrpvfxfvwvbh3qq
Processor virtualization and split compilation for heterogeneous multicore embedded systems
2010
Proceedings of the 47th Design Automation Conference on - DAC '10
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2015; you can also visit the original URL.
The file type is application/pdf.
Embedded multiprocessors have always been heterogeneous, driven by the power-efficiency and compute-density of hardware specialization. ...
steps in a split optimization process. ...
to run not only on the host processor, but also on the more powerful on-chip accelerators; • to streamline the deployment of applications in enterprise networks or in cloud-computing environments, where ...
doi:10.1145/1837274.1837303
dblp:conf/dac/CohenR10
fatcat:2xh5ftj5ynf5loakm3zghqapoa
D3.1: Programming Model Specification
2021
Zenodo
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
Section 1 describes the XANDAR design methodology, which is the procedure for developing software for embedded systems according to the XANDAR approach. ...
It is based on the XANDAR process as described in deliverable 2.1. ...
The advanced embedded multiprocessor system-on-chip architectures allow implementation of mixed-critical software applications and provide on-chip security mechanisms to segregate and protect system resources ...
doi:10.5281/zenodo.6539487
fatcat:p3htxnu6cfczvm7b7gkyfewz3i
Prototyping hardware support for irregular applications
2013
Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation Methods and Tools - RAPIDO '13
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
However, current FPGA toolchains that allow quick deployment of system-on-chip designs still have troubles when implementing multiprocessor designs. ...
We present an initial study on the tradeoffs of the platform, showing how prototyping can be effective, but also underlining the aspects that still need to be improved in the toolchain to allow better ...
Specifically, the RAMP project [20] proposed the use of this approach to perform system level research of multiprocessor designs. ...
doi:10.1145/2432516.2432520
dblp:conf/rapido/CerianiSTV13
fatcat:hgxonz26irerdhz3maramenavy
« Previous
Showing results 1 — 15 out of 207 results