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Tolerating operational faults in cluster-based FPGAs
2000
Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays - FPGA '00
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In addition to providing functional density, FPGAs provide a level of fault tolerance generally not found in mask-programmable devices by including the capability to reconfigure around operational faults ...
In this paper, incremental CAD techniques are described that allow functional recovery of FPGA design configurations in the presence of single or multiple operational faults. ...
In Section 2 a description of the issues involved in providing FPGA fault tolerance is presented. Section 3 describes previous work in FPGA fault tolerance and overviews cluster-based FPGAs. ...
doi:10.1145/329166.329205
dblp:conf/fpga/LakamrajuT00
fatcat:kkxjayfu5nhp5kto2lult26x5a
Design Approach for Fault Tolerance in FPGA Architecture
2011
International Journal of VLSI Design & Communication Systems
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In addition to providing functional density, FPGAs provide a level of fault tolerance generally not found in mask-programmable devices by including the capability to reconfigure around operational faults ...
In regular structure like FPGA, redundancy is commonly used for fault tolerance. ...
In regular structure like FPGA, redundancy is commonly used for fault tolerance. ...
doi:10.5121/vlsic.2011.2108
fatcat:nes75pqxgfdjbgd5zo6ah2j4s4
Fault tolerant methods for reliability in FPGAs
2008
2008 International Conference on Field Programmable Logic and Applications
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This paper provides the first comprehensive survey of fault detection methods and fault tolerance schemes specifically for FPGAs, with the goal of laying a strong foundation for future research in this ...
Reliability and process variability are serious issues for FPGAs in the future. ...
tolerating faults in logic clusters exists if the cluster can be reconfigured to work around the fault [44] . ...
doi:10.1109/fpl.2008.4629973
dblp:conf/fpl/StottSC08
fatcat:gxrojxqwqjco7f7eejzyj2p4uq
An adaptive method to tolerate soft errors in SRAM-based FPGAs
2011
Scientia Iranica. International Journal of Science and Technology
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Abstract In this paper, we present an adaptive method that is a combination of SEU-avoidance in CAD flow and adaptive redundancy to tolerate soft error effects in SRAM-based FPGAs. ...
KEYWORDS SRAM-based FPGA; Soft error; Error propagation probability; System failure rate. ...
Having smaller feature size, higher integration level, smaller noise margin and lower operating voltage make the tolerance to transient faults a key challenge in SRAM-based FPGAs [8] . ...
doi:10.1016/j.scient.2011.08.024
fatcat:m362uwmwbza4rjfwymdit3igou
FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders
2013
VLSI design (Print)
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This paper examines fault tolerant adder designs implemented on FPGAs which are inspired by the methods of modular redundancy, roving, and gradual degradation. ...
The TMR-RCA is found to have the best delay performance and most efficient resource utilization for an FPGA fault-tolerant implementation due to the simplicity of the approach and the use of the fast-carry ...
For example, cluster reconfiguration aims to tolerate faults which occur in clusters [21] , while the goal of pebble shifting is to minimize the area and timing overhead [22] . ...
doi:10.1155/2013/382682
fatcat:lxdc2osqbjak3acjf7gea4ls6m
Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC
2015
IEICE transactions on information and systems
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In this evaluation, we compared the performances of conventional FPGAs and the proposed fault-tolerant FPGA architectures. ...
At the same time, our FPGA shows a higher fault tolerant performance. ...
Acknowledgements This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc. and Cadence Design Systems, Inc. ...
doi:10.1587/transinf.2014rcp0009
fatcat:r7jzf4t24vab7f6psnjfokmcmy
Fault tolerant placement and defect reconfiguration for nano-FPGAs
2008
2008 IEEE/ACM International Conference on Computer-Aided Design
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This is the first work (to the best of our knowledge) that addresses the problem of fault tolerance for nano-FPGAs at the placement stage; fault tolerant placements are generated that are amenable to fast ...
In addition, our study of the fault reconfiguration problem shows it is NP-Complete, and we propose a fast scheme for achieving a good reconfiguration solution for a random or clustered fault map. ...
RELATED WORK AND CONCLUSIONS Prior work on FPGA fault tolerance methods can be broadly categorized into two groups, based on the level of abstraction at which faults are tolerated [1] . ...
doi:10.1109/iccad.2008.4681655
dblp:conf/iccad/AgarwalCT08
fatcat:6g3tvnho6bckpjgqzxm7z4ihwm
Guest Editorial Special Section on Configurable Computing Design—II: Hardware Level Reconfiguration
2008
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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The first paper of this group, "Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays," by P. ...
Zipf, deals with the realization of a fault tolerance technique which consists of three parts: fault detection, fault reconfiguration, and fault recovery. ...
Also, his interests include computer networking, mobile computing, and web-based technologies. ...
doi:10.1109/tvlsi.2007.914084
fatcat:v2hlvtqxgba6rplso6fgafve3a
CRUSADE
1999
Proceedings of the conference on Design, automation and test in Europe - DATE '99
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We also show how our co-synthesis algorithm can be easily extended to consider fault-detection and fault-tolerance. ...
Application of CRUSADE and its fault tolerance extension, CRUSADE-FT to several real-life large examples (up to 7400 tasks) from mobile communication network base station, video distribution router, a ...
Co-Synthesis of Fault Tolerant Systems Embedded systems employed in critical application demand fault tolerance which provides fault detection followed by error-recovery. ...
doi:10.1145/307418.307461
fatcat:6dcuxlzuc5egzhunhzhnitie5y
The survivability of design-specific spare placement in FPGA architectures with high defect rates
2013
ACM Transactions on Design Automation of Electronic Systems
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We address the problem of optimizing fault tolerance in FPGA architectures with high defect rates (such as nano-FPGAs) without significantly degrading performance. ...
Our methods address fault tolerance during the placement and reconfiguration stages of FPGA programming. ...
Spare supply computation takes constant time per CLB and is performed for each CLB in the FPGA, making it an O((kn) 4/3 ) operation. ...
doi:10.1145/2442087.2442104
fatcat:p36tippmdbbzlpxq4zwevhy554
Author index
2007
2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)
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Support for Reconfi gurable
Multithreaded Processors in Program-
mable Communication Systems
Performance Evaluation of Adaptive
Routing Algorithms for achieving Fault
Tolerance in NoC Fabrics
Evaluation ...
Memory Layout
Performance Evaluation of Probe-Send
Fault-tolerant Network-on-chip Router
A memcpy Hardware Accelerator Solu-
tion for Non Cache-line Aligned Copies
Evaluation of a tightly coupled ...
doi:10.1109/asap.2007.4459300
fatcat:lbxlom2lkrf2jf3q5c56uwiuea
Fault-tolerant Mechatronic Systems Development: a Biologically-inspired Approach
2015
Recent Innovations in Mechatronics
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In such cases it looks a high demand for more reliable, safety and fault-tolerant mechatronic systems development. ...
The paper presents a biologicallyinspired computing system based on a Field Programmable Gate Array (FPGA) network developed for high reliability mechatronic applications. ...
Let's consider in this cluster the fault of the active cell A. ...
doi:10.17667/riim.2015.1-2/19
fatcat:anfbcxzdhvbefbp6sj23esczk4
Design and Validation for FPGA Trust under Hardware Trojan Attacks
2016
IEEE Transactions on Multi-Scale Computing Systems
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field operation. ...
In this paper, we present a taxonomy of FPGA-specific hardware Trojan attacks based on activation and payload characteristics along with Trojan models that can be inserted by an attacker. ...
ACKNOWLEDGMENTS This work is funded in part by US National Science Foundation (NSF) grants 1603475, 1603483, and 1603480. ...
doi:10.1109/tmscs.2016.2584052
fatcat:akd6wzxh7fgmric4ibdqxkd5eu
System fault-tolerance analysis of COTS-based satellite on-board computers
2014
Microelectronics Journal
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For the first time we can compare the efficiency of fault-tolerance techniques implemented in software and Field-Programmable Gate Array (FPGA). ...
In this paper we present a statistical simulation approach for fault-tolerance analysis of satellite On-Board Computers (OBCs) that are based on Commercial Off-The-Shelf (COTS) components. ...
SRAM-based FPGA type is not considered in this work. In Section 5 we propose the generalized simulation approach for the fault-tolerance analysis with SEU fault-model. ...
doi:10.1016/j.mejo.2014.01.007
fatcat:akubqk74znflfg76opvnel2kcy
Software fault tolerance methodology and testing for the embedded PowerPC
2011
2011 Aerospace Conference
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In this paper we describe our software-based fault tolerance strategies for PowerPC devices embedded within Xilinx Virtex 4 FX60 FPGAs. ...
Our work targets scientific applications operating on space-based FPGA architectures consisting of an FPGA and a radiation-hardened controller. ...
RELATED WORK When operating in a space environment, Xilinx SRAM based FPGAs, like other SRAM memories, are susceptible to radiation induced Single Event Upsets (SEUs). ...
doi:10.1109/aero.2011.5747460
fatcat:oh3owy5yrjaivmp2xp3zdfqeaa
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