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TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory

Jayaram Bobba, Neelam Goyal, Mark D. Hill, Michael M. Swift, David A. Wood
2008 2008 International Symposium on Computer Architecture  
TokenTM executes small transactions fast, executes concurrent large transactions with no penalty to nonconflicting transactions, and gracefully handles paging, context switching, and System-V-style shared  ...  Current hardware transactional memory systems seek to simplify parallel programming, but assume that large transactions are rare, so it is acceptable to penalize their performance or concurrency.  ...  TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory To this end, we propose a fast unbounded HTM called TokenTM.  ... 
doi:10.1109/isca.2008.24 dblp:conf/isca/BobbaGHSW08 fatcat:f2cpuzdfabdixap4n6lreva7pa

EcoTM: Conflict-aware Economical Unbounded Hardware Transactional Memory

Saša Tomić, Ege Akpinar, Adrian Cristál, Osman Unsal, Mateo Valero
2013 Procedia Computer Science  
In this paper we explore Hardware support for TM (HTM). In particular, we explore how HTM can efficiently support transactions of nearly unlimited size.  ...  For this purpose we propose EcoTM, an economical unbounded HTM that improves the efficiency of conflict detection between very large transactions by activating conflict-detection logic only for potentially-conflicting  ...  Whereas commonly proposed HTMs are efficient, they typically work with transactions up to a few cache lines large (i.e. best-effort HTMs).  ... 
doi:10.1016/j.procs.2013.05.190 fatcat:jkevqwwj75cpbozk7w7hfk2eby

Transactional memory

Håkan Grahn
2010 Journal of Parallel and Distributed Computing  
Transactional memory implementation proposals exist for both hardware and software, as well as hybrid solutions.  ...  the state-of-the-art in transactional memory research.  ...  Using these two mechanisms TokenTM is able to perform fast conflict detection between an arbitrary number of memory blocks, execute small transactions fast, and execute large concurrent transactions without  ... 
doi:10.1016/j.jpdc.2010.06.006 fatcat:s3qswzin6jhoneph7taqsnxoxe

Version management alternatives for hardware transactional memory

Marc Lupon, Grigorios Magklis, Antonio González
2008 Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08  
Hardware Transactional Memory (HTM) implements these mechanisms in silicon to obtain better results than fine-grain locking solutions.  ...  Transactional Memory is a promising parallel programming model that addresses the programmability issues of lockbased applications using mechanisms that are transparent to developers.  ...  The issue with finite hardware is that large transactions may overflow the buffering space.  ... 
doi:10.1145/1509084.1509094 fatcat:t3qtssordnh47i7db7yqusyssa

Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading

Leo Porter, Bumyong Choi, Dean M. Tullsen
2009 2009 18th International Conference on Parallel Architectures and Compilation Techniques  
This research demonstrates that coming support for hardware transactional memory can be leveraged to significantly reduce the cost of implementing true speculative multithreading.  ...  The result is a unified memory architecture capable of effective support for transactional parallel workloads and efficient speculative multithreading.  ...  Prior research has examined both software transactional memory [10] - [12] and hardware transactional memory [1] - [9] .  ... 
doi:10.1109/pact.2009.37 dblp:conf/IEEEpact/PorterCT09 fatcat:4ldki34k4ncyjc4sfukl2gqbsy

FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery

Marc Lupon, Grigorios Magklis, Antonio Gonzalez
2009 2009 18th International Conference on Parallel Architectures and Compilation Techniques  
Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored.  ...  Lazy systems that buffer new values in specialized hardware offer complex and inefficient solutions to handle hardware overflows, which are common in applications with coarse-grain transactions.  ...  INTRODUCTION A high performance Transactional Memory (TM) system must provide an efficient implementation of the mechanisms that guarantee transactional semantics, offering fast execution in case of infrequent  ... 
doi:10.1109/pact.2009.19 dblp:conf/IEEEpact/LuponMG09 fatcat:gzg62rdxifh65nrc6blmu4fu7y

Transactional Memory, 2nd edition

Tim Harris, James Larus, Ravi Rajwar
2010 Synthesis Lectures on Computer Architecture  
The hardware executes these transactions and enforces correct execution by detecting any memory dependence violations between the threads.  ...  Since the TokenTM metadata implementation is a conservative summary of the actual metadata,TokenTM also records these tokens in memory (in a manner reminiscent to memory versioning in LogTM).  ...  He has worked on concurrent algorithms and transactional memory for over ten years, most recently, focusing on the implementation of STM for multi-core computers and the design of programming language  ... 
doi:10.2200/s00272ed1v01y201006cac011 fatcat:25d3gvp5zrfqlgpzdzknqouofi

SI-TM

Heiner Litz, David Cheriton, Amin Firoozshahian, Omid Azizi, John P. Stevenson
2014 Proceedings of the 19th international conference on Architectural support for programming languages and operating systems - ASPLOS '14  
Our implementation utilizes a memory controller that supports multiversion memory, to efficiently support snapshotting in hardware.  ...  Conventional transactional memory realizations not only pessimistically abort transactions on every read-write conflict but also because of false sharing, cache evictions, TLB misses, page faults and interrupts  ...  We are grateful to Timothy Harris, Michael Chan, Ricardo Dias, Tor Aamodt, Stephan Diestelhorst and the anonymous reviewers for their useful feedback on earlier versions of this manuscript.  ... 
doi:10.1145/2541940.2541952 dblp:conf/asplos/LitzCFAS14 fatcat:er7rsyd4f5cs5i3irx6ijek6bq

OmniOrder: Directory-based conflict serialization of transactions

Xuehai Qian, Benjamin Sahelices, Josep Torrellas
2014 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)  
Atomic blocks can be demarcated in software as in Transactional Memory (TM) or dynamically generated by the hardware as in aggressive implementations of strict memory consistency.  ...  Effective execution of atomic blocks of instructions (also called transactions) can enhance the performance and programmability of multiprocessors.  ...  Wait-n-GoTM [16] is based on TokenTM [8] , and uses a hardware-software combination to execute conflicting atomic blocks concurrently.  ... 
doi:10.1109/isca.2014.6853223 dblp:conf/isca/QianST14 fatcat:4thq2r6rcbhvxamkomyys73zwq

OmniOrder

Xuehai Qian, Benjamin Sahelices, Josep Torrellas
2014 SIGARCH Computer Architecture News  
Atomic blocks can be demarcated in software as in Transactional Memory (TM) or dynamically generated by the hardware as in aggressive implementations of strict memory consistency.  ...  Effective execution of atomic blocks of instructions (also called transactions) can enhance the performance and programmability of multiprocessors.  ...  Wait-n-GoTM [16] is based on TokenTM [8] , and uses a hardware-software combination to execute conflicting atomic blocks concurrently.  ... 
doi:10.1145/2678373.2665734 fatcat:khqohcx6dnbavmqpov7zo2im7e

Implementation tradeoffs in the design of flexible transactional memory support

Arrvindh Shriraman, Sandhya Dwarkadas, Michael L. Scott
2010 Journal of Parallel and Distributed Computing  
Finally, we compare the use of an aggressive hardware controller (as used in the base FlexTM design) to manage and to access any speculative transaction state overflowed from the cache, to a hardware-software  ...  hardware to manage transactional state and to track conflicts.  ...  It has a varied mix of large and small transactions with varying types and levels of conflicts [18] .  ... 
doi:10.1016/j.jpdc.2010.03.006 fatcat:6im5tb4ihfblhaz3t5ibyjsu3y

Reconstructing Hardware Transactional Memory for Workload Optimized Systems [chapter]

Kunal Korgaonkar, Prabhat Jain, Deepak Tomar, Kashyap Garimella, Veezhinathan Kamakoti
2011 Lecture Notes in Computer Science  
With the continuity of Moore's law in the multicore era and the emerging cloud computing, parallelism has been pervasively available almost everywhere, from traditional processor pipelines to large-scale  ...  We accepted 13 papers out of 40 submissions, presenting an acceptance rate of 32.5%.  ...  .: TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory. In: Proc. of Int.  ... 
doi:10.1007/978-3-642-24151-2_1 fatcat:32cx745cn5cfdm5sbeah6eyiey

Large-scale transactional execution of FPGA-accelerated irregular applications [article]

Xiaoyu Ma
2017
List of Tables xiv List of Figures xv Chapter 1. Introduction Transactional Memory (TM) .  ...  TokenTM [45] uses the abstraction of tokens to precisely track conflicts on an unbounded number of memory blocks and, therefore, executes concurrent large transactions with no penalty to non-conflicting  ...  Too many or too large transactions can cause an overflow of hardware buffers for the transactional states.  ... 
doi:10.15781/t28c9rm3c fatcat:rb3cqcdbjvanzitv6l7uxxjim4