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Registers [article]

Paul M.B. Vitanyi
2006 arXiv   pre-print
., Springer, To appear. Synonyms: Wait-free registers, wait-free shared variables, asynchronous communication hardware.  ...  Problem Definition: Consider a system of asynchronous processes that communicate among themselves by only executing read and write operations on a set of shared variables (also known as shared registers  ...  Lamport did not consider constructions of shared variables with more than one writer or reader.  ... 
arXiv:cs/0612025v1 fatcat:fm7poejxv5gcnnfdhpfqycsule

Atomic multireader register [chapter]

Lefteris M. Kirousis, Evangelos Kranakis, Paul M. B. Vitányi
1988 Lecture Notes in Computer Science  
This closes the last gap in the atomic shared register area.  ...  Together with some earlier constructions these results show how to construct atomic, multireader, multiwriter registers frombasicallyelementary hardware like flip-flops.  ...  (Note that each matrix entry needs to stores the vector W and a value v .) Theorem.  ... 
doi:10.1007/bfb0019809 fatcat:ryv6p4whwbejtk4au5o274u5ti

Flexible register management using reference counting

Steven Battle, Andrew D. Hilton, Mark Hempstead, Amir Roth
2012 IEEE International Symposium on High-Performance Comp Architecture  
Columns are NOR'ed together to create a bitvector free list from which registers are allocated using priority encoders.  ...  We describe reference counting designs that support micro-architectural techniques including register file power gating, dynamic register move elimination, register file checkpointing, and latency tolerant  ...  Hardwired "register" p0 does not need to be reference counted because it is not allocated or freed.  ... 
doi:10.1109/hpca.2012.6169033 dblp:conf/hpca/BattleHHR12 fatcat:ugnn5rhmizg7xd5nmo2aenj6cu

Randomized registers and iterative algorithms

Hyunyoung Lee, Jennifer L. Welch
2005 Distributed computing  
We show that these specifications are implemented by the probabilistic quorum algorithm of Malkhi, Reiter, Wool, and Wright, and we illustrate how to program with such registers in the framework of Bertsekas  ...  We present three different specifications of a read-write register that may occasionally return out-of-date values -namely, a (basic) random register, a P -random register, and a monotone random register  ...  Acknowledgments: We thank the anonymous referees for many helpful comments, especially for bringing [6] to our attention and for pointing out an error in the earlier proof of Theorem 13.  ... 
doi:10.1007/s00446-004-0106-3 fatcat:uwkgceicwvb6jlivuhxcxbm4qm

Fork-consistent constructions from registers

Matthias Majuntke, Dan Dobre, Neeraj Suri
2011 Proceedings of the 30th annual ACM SIGACT-SIGOPS symposium on Principles of distributed computing - PODC '11  
A read-modify-write object is much more powerful than a shared memory made of so-called registers, which lie in the weakest class of all shared objects in this hierarchy.  ...  a weakly fork-linearizable emulation of a shared memory that ensures waitfreedom when the registers are correct.  ...  Standard methods implementing robust shared registers from fault-prone base registers show how to tolerate up to a fraction of Byzantine base registers [11] .  ... 
doi:10.1145/1993806.1993837 dblp:conf/podc/MajuntkeDS11 fatcat:qcmsqak6ofhv3lejifypnvsdo4

Fork-Consistent Constructions from Registers [chapter]

Matthias Majuntke, Dan Dobre, Christian Cachin, Neeraj Suri
2011 Lecture Notes in Computer Science  
A read-modify-write object is much more powerful than a shared memory made of so-called registers, which lie in the weakest class of all shared objects in this hierarchy.  ...  a weakly fork-linearizable emulation of a shared memory that ensures waitfreedom when the registers are correct.  ...  Standard methods implementing robust shared registers from fault-prone base registers show how to tolerate up to a fraction of Byzantine base registers [11] .  ... 
doi:10.1007/978-3-642-25873-2_20 fatcat:zguzas3ctbbi7cjdctxpf6i7qq

Physical register reference counting

A. Roth
2008 IEEE computer architecture letters  
Several recently proposed techniques including CPR (Checkpoint Processing and Recovery) and NoSQ (No Store Queue) rely on reference counting to manage physical registers.  ...  Comments Abstract-Several recently proposed techniques including CPR (Checkpoint Processing and Recovery) and NoSQ (No Store Queue) rely on reference counting to manage physical registers.  ...  ACKNOWLEDGMENTS The author thanks Adam Butts, Milo Martin, Vlad Petric, and Tingting Sha for discussions about physical register reference counting and for comments on this manuscript.  ... 
doi:10.1109/l-ca.2007.15 fatcat:asvvav3ndvaufd6my6gci6cpt4

Cost effective physical register sharing

Arthur Perais, Andre Seznec
2016 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)  
However, register sharing requires modifications to the register reclaiming process: Committing a single instruction does not guarantee that the physical register allocated to the previous mapping of its  ...  Sharing a physical register between several instructions is needed to implement several microarchitectural optimizations.  ...  Not All Registers Are Shared We base our final reference counting scheme on the intuition that if a snapshot of the register file had to be taken, most would either be referenced one time only or be free  ... 
doi:10.1109/hpca.2016.7446105 dblp:conf/hpca/PeraisS16 fatcat:wukab2hppvdkled3oytqv5z3im

Machine-independent register allocation

Richard L. Sites
1979 Proceedings of the 1979 SIGPLAN symposium on Compiler construction - SIGPLAN '79  
Fields in variant records, which may overlap or share storage, have been mapped into overlapping or identical <offset, length> pairs.  ...  not practical to calculate a register number as a variable subscript.  ... 
doi:10.1145/800229.806973 dblp:conf/sigplan/Sites79 fatcat:acbn4tkufvcdvlvcnvmsob6exu

Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors

Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
This paper presents a novel register file architecture, which has single ported cells and asymmetric interfaces to the memory and to the datapath.  ...  The novel architecture presented is shown to obtain energy gains of upto 10X with respect to conventional multi-ported register file over the different benchmarks. 1 The details of the memory design and  ...  The datapath may or may not support sub-word parallelism similar to state of the art processor engines like Altivec, MMX or SSE2.  ... 
doi:10.1109/date.2007.364435 dblp:conf/date/RaghavanLJCVC07 fatcat:mcnd5ud4o5cobprszkgaknv7xm

Register Allocation and Binding for Low Power

Jui-Ming Chang
1995 Proceedings - Design Automation Conference  
Based on the assumption that the joint pdf (probability density function) of the primary input random variables is known or that a suciently large number of input vectors has been given, the register assignment  ...  This paper describes a technique for calculating the switching activity of a set of registers shared by dierent data values.  ...  During the register allocation and assignment, data values (arcs in the data ow graph) can share the same physical register if their life times do not overlap.  ... 
doi:10.1109/dac.1995.250019 fatcat:pq5mjtizyrdlri7hz34i2jmc7e

Register allocation and binding for low power

Jui-Ming Chang, Massoud Pedram
1995 Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95  
Based on the assumption that the joint pdf (probability density function) of the primary input random variables is known or that a suciently large number of input vectors has been given, the register assignment  ...  This paper describes a technique for calculating the switching activity of a set of registers shared by dierent data values.  ...  During the register allocation and assignment, data values (arcs in the data ow graph) can share the same physical register if their life times do not overlap.  ... 
doi:10.1145/217474.217502 dblp:conf/dac/ChangP95 fatcat:pzx3mtjkdfg6be3x7i652upogu

Communication-minimizing 2D convolution in GPU registers

Forrest N. Iandola, David Sheffield, Michael J. Anderson, Phitchaya Mangpo Phothilimthana, Kurt Keutzer
2013 2013 IEEE International Conference on Image Processing  
To reduce memory communication, we reorganize the convolution algorithm to prefetch image regions to register, and we do more work per thread with fewer threads.  ...  To enable portability to future architectures, we implement a convolution autotuner that sweeps the design space of memory layouts and loop unrolling configurations.  ...  ACKNOWLEDGEMENTS The authors would like to thank James Demmel, Leonid Oliker, Pavan Yalamanchili, Yun-Ta Tsai, and Kari Pulli.  ... 
doi:10.1109/icip.2013.6738436 dblp:conf/icip/IandolaSAPK13 fatcat:lnmb2fwaizfkndjkkhtzfgyw3y

Auditable Register Emulations [article]

Vinicius V. Cogo, Alysson Bessani
2020 arXiv   pre-print
In this work, we initiate the study of auditable storage emulations, which provide the capability for an auditor to report the previously executed reads in a register.  ...  We also show that signing read requests overcomes the lower bound of weak auditability, while totally ordering operations or using non-fast reads enables strong auditability.  ...  It means readers do not need to execute low-level reads in all n base objects to obtain these τ blocks. Base objects in this work are loggable R/W registers. Loggable R/W Register Specification.  ... 
arXiv:1905.08637v2 fatcat:abux5fnj3neljacnaobnghnr4u

On Register Linearizability and Termination [article]

Vassos Hadzilacos, Xing Hu, Sam Toueg
2021 arXiv   pre-print
MWMR registers do not have strongly linearizable implementations from SWMR registers.  ...  In contrast to the impossibility result mentioned above, we prove that write strongly-linearizable MWMR registers are implementable from SWMR registers.  ...  (g) Then p 2 , p 3 , . . . , p n−1 execute line 24, and find that the condition (u 1 = ⊥ or u 2 = ⊥ or c = ⊥) of this line does not hold, and so they proceed to execute line 27.  ... 
arXiv:2102.13242v1 fatcat:cy6dzy6vpffplf2vcjgo363khq
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