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Timing-driven routing for FPGAs based on Lagrangian relaxation

Seokjin Lee, D. F. Wong
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
TIMING-DRIVEN FPGA ROUTING i W ¦ g b ¤ & ¢ R ¢ 6 ¨ ¤ § ¦ V p I ! ¦ ¢ 6 ¤ & " g b ä ¤ § 3 4 ¤ & ¦ B ! A W " 0 ¤ § X Y ¦ P R Q T S @ ¡ v !  ...  ¤ % 8 ¦ 3 g D $ C ¤ § ( $ § ¤ § ¢ h 4.1 Lagrangian Relaxatioņ $ & % 8 ẗ b ` ¤ § 3 4 ¤ & ¦ B ¦ ¢ 6 7 % 8 ¤ § ¦ © ¢ 1 ¤ § ¦ s b 8 ¤ & B ! ¤ § ¦ d % ! $ T ( !  ... 
doi:10.1145/505430.505431 fatcat:ds5i6r4jgjhqrkxtepnpsgaq6m

Timing-driven routing for FPGAs based on lagrangian relaxation

Seokjin Lee, M.D.F. Wong
2003 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
TIMING-DRIVEN FPGA ROUTING i W ¦ g b ¤ & ¢ R ¢ 6 ¨ ¤ § ¦ V p I ! ¦ ¢ 6 ¤ & " g b ä ¤ § 3 4 ¤ & ¦ B ! A W " 0 ¤ § X Y ¦ P R Q T S @ ¡ v !  ...  ¤ % 8 ¦ 3 g D $ C ¤ § ( $ § ¤ § ¢ h 4.1 Lagrangian Relaxatioņ $ & % 8 ẗ b ` ¤ § 3 4 ¤ & ¦ B ¦ ¢ 6 7 % 8 ¤ § ¦ © ¢ 1 ¤ § ¦ s b 8 ¤ & B ! ¤ § ¦ d % ! $ T ( !  ... 
doi:10.1109/tcad.2003.809645 fatcat:idkktzsbzbgz3hx2dgjymhfjhm

Timing-driven routing for FPGAs based on Lagrangian relaxation

Seokjin Lee, D. F. Wong
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
TIMING-DRIVEN FPGA ROUTING i W ¦ g b ¤ & ¢ R ¢ 6 ¨ ¤ § ¦ V p I ! ¦ ¢ 6 ¤ & " g b ä ¤ § 3 4 ¤ & ¦ B ! A W " 0 ¤ § X Y ¦ P R Q T S @ ¡ v !  ...  ¤ % 8 ¦ 3 g D $ C ¤ § ( $ § ¤ § ¢ h 4.1 Lagrangian Relaxatioņ $ & % 8 ẗ b ` ¤ § 3 4 ¤ & ¦ B ¦ ¢ 6 7 % 8 ¤ § ¦ © ¢ 1 ¤ § ¦ s b 8 ¤ & B ! ¤ § ¦ d % ! $ T ( !  ... 
doi:10.1145/505388.505431 dblp:conf/ispd/LeeW02 fatcat:cqperdypzzgvrhfket5t3pwy7i

A min-cost flow based detailed router for FPGAs

Seokjin Lee, Yongseok Cheon, M.D.F. Wong
2003 ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)  
For further improvement, we adopt an iterative refinement scheme based on the Lagrangian relaxation technique.  ...  In this paper, we present a detailed routing algorithm for FPGAs based on min-cost flow computations.  ...  To avoid ordering problem of selecting LUTs, we adopt an iterative refinement scheme based on Lagrangian relaxation.  ... 
doi:10.1109/iccad.2003.159716 fatcat:32q4i6cfj5bhxn3iqidjrmbsui

NWR: Net Weighing Based Timing Driven Routing Algorithm

Geetanjali Udgirkar, Dr. G. lndumathi
2018 Indian Journal of Science and Technology  
Timing driven routing with net weighting approach has not been explored in the past. Findings: We present two novel timing driven routing algorithm which is based on weighting of the critical nets.  ...  Methods/Statistical analysis: Net weighing algorithms for timing driven placement are effective way of optimizing delays during routing of designs.  ...  Acknowledgements We would like to thank Department of Electronics and Communication Engineering, Cambridge Institute of Technology, Bangalore for providing the resources to conduct the experiments.  ... 
doi:10.17485/ijst/2018/v11i19/123230 fatcat:5rx44rh5sbb4dhxzu7ng4lxrou

ParaLarH: Parallel FPGA Router based upon Lagrange Heuristics [article]

Rohit Agrawal, Kapil Ahuja, Dhaarna Maheshwari, Akash Kumar
2020 arXiv   pre-print
Routing of the nets in Field Programmable Gate Array (FPGA) design flow is one of the most time consuming steps.  ...  Although Versatile Place and Route (VPR), which is a commonly used algorithm for this purpose, routes effectively, it is slow in execution.  ...  The constraints are relaxed by introducing the Lagrangian multipliers.  ... 
arXiv:2010.11893v1 fatcat:qt74xfwrefh7jesr3xe4eicjr4

Net reordering and multicommodity flow based global routing for FPGAs

Cristinel Ababei, Rajesh G. Kavasseri, Mohammad A. Zare
2014 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)  
The most popular algorithm for solving the routing problem for field programmable gate arrays (FPGAs) has virtually remained the same for the past two decades.  ...  Also, we alter the cost calculation during wave expansions for two-pin nets based on the global routing solution obtained by solving an equivalent multicommodity flow problem.  ...  To alleviate the block ordering problem, they use an iterative refinement scheme based on Lagrangian relaxation.  ... 
doi:10.1109/reconfig.2014.7032540 dblp:conf/reconfig/AbabeiKZ14 fatcat:wn5qg3hulbe4pj24fngjnujwoi

ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method

Rohit Agrawal, Kapil Ahuja, Chin Hau Hoo, Tuan Duy Anh Nguyen, Akash Kumar
2019 Electronics  
In the field programmable gate array (FPGA) design flow, one of the most time-consuming steps is the routing of nets. Therefore, there is a need to accelerate it.  ...  We obtain the same value for the total wire length as by ParaLaR, which is 49 % better on an average than that obtained by VPR.  ...  In the field programmable gate array (FPGA) [1, 2] design flow, the routing of nets (which are a collection of two or more interconnected components) is one of the most time-consuming steps.  ... 
doi:10.3390/electronics8121439 fatcat:6ep3ytqpjvdbxhbdpc4uvpugeq

2009 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 28

2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
., +, TCAD Sept. 2009 1348-1358 Gate Sizing by Lagrangian Relaxation Revisited.  ...  Vytyaz, I., +, TCAD May 2009 609-622 Gate Sizing by Lagrangian Relaxation Revisited.  ... 
doi:10.1109/tcad.2009.2036802 fatcat:hxyu2mmrnzfnbi6qlt6bklkgku

2021 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 40

2021 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The Author Index contains the primary entry for each item, listed under the first author's name.  ...  Inside Lagrangian Relaxation-Based Optimization.  ...  ., +, TCAD Dec. 2021 2542-2555 Clocks A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing. Hsu, C., +, Relaxation-Based Optimization.  ... 
doi:10.1109/tcad.2021.3136047 fatcat:ppooj4g65nc2zonj7szclerc2y

Length-matching routing for high-speed printed circuit boards

M.M. Ozdal, M.D.F. Wong
2003 ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)  
As the clock frequencies used in industrial applications increase, the timing requirements imposed on routing problems become tighter.  ...  Our approach is to use a Lagrangian relaxation framework to allocate extra routing resources around nets simultaneously during routing them.  ...  Lagrangian Relaxation Based Resource Allocation Lagrangian relaxation is a general technique for solving optimization problems with difficult constraints.  ... 
doi:10.1109/iccad.2003.159717 fatcat:hw5np76gi5dyxcvyt6fkoelope

Board-level multiterminal net assignment for the partial cross-bar architecture

Xiaoyu Song, W.N.N. Hung, A. Mishchenko, M. Chrzanowska-Jeske, A. Kennings, A. Coppola
2003 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in Clos-Folded FPGA based logic emulation systems.  ...  The approach transforms the FPGA board-level routing task into a single, large Boolean equation with the property that any assignment of input variables that satisfies the equation specifies a valid routing  ...  To handle routing constraints that may arise from certain timing requirement, Mak and Wong [11] proposed a performance-driven routing algorithm for the board-level routing problem that can handle additional  ... 
doi:10.1109/tvlsi.2003.812322 fatcat:co7brzurtzcy3h2jyy4hzkaory

Board-level multiterminal net assignment

Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Alan Coppola, Andrew Kennings
2002 Proceedings of the 12th ACM Great Lakes Symposium on VLSI - GLSVLSI '02  
The paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in Clos-Folded FPGA based logic emulation systems.  ...  The approach transforms the FPGA board-level routing task into a single, large Boolean equation with the property that any assignment of input variables that satisfies the equation specifies a valid routing  ...  To handle routing constraints that may arise from certain timing requirement, Mak and Wong [11] proposed a performance-driven routing algorithm for the board-level routing problem that can handle additional  ... 
doi:10.1145/505306.505335 dblp:conf/glvlsi/SongHMCCK02 fatcat:kqbs6krqovamxbjrne3hyeffli

Board-level multiterminal net assignment

Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Alan Coppola, Andrew Kennings
2002 Proceedings of the 12th ACM Great Lakes Symposium on VLSI - GLSVLSI '02  
The paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in Clos-Folded FPGA based logic emulation systems.  ...  The approach transforms the FPGA board-level routing task into a single, large Boolean equation with the property that any assignment of input variables that satisfies the equation specifies a valid routing  ...  To handle routing constraints that may arise from certain timing requirement, Mak and Wong [11] proposed a performance-driven routing algorithm for the board-level routing problem that can handle additional  ... 
doi:10.1145/505334.505335 fatcat:o5ogprsganbtpolodaoe2marwu

A Routing Approach to Reduce Glitches in Low Power FPGAs

Quang Dinh, Deming Chen, Martin D. F. Wong
2010 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
To the best of our knowledge, this is the first glitch-aware routing algorithm for FPGAs.  ...  This approach involves finding alternative routes for earlyarriving signals, so that signal arrival times at LUTs are aligned and no glitches are generated.  ...  Many recently published FPGA routing algorithms are based on the negotiated congestion mechanism proposed in the PathFinder paper [8] .  ... 
doi:10.1109/tcad.2009.2035564 fatcat:dl5qtbagv5hvjohu7jg523azxi
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