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Timing-driven placement for FPGAs

Alexander Marquardt, Vaughn Betz, Jonathan Rose
2000 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays - FPGA '00  
In this paper we introduce a new Simulated Annealingbased timing-driven placement algorithm for FPGAs. This paper has three main contributions.  ...  timing-driven placement.  ...  A timing-driven router can only produce routings that are as good as the placement on which the routing is performed, so to extract more speed out of an FPGA it is essential that timing-driven placement  ... 
doi:10.1145/329166.329208 dblp:conf/fpga/MarquardtBR00 fatcat:2l7tcwllujdpxjwgu4ku7ebkbq

Simultaneous Timing Driven Clustering and Placement for FPGAs [chapter]

Gang Chen, Jason Cong
2004 Lecture Notes in Computer Science  
Traditional placement algorithms for FPGAs are normally carried out on a fixed clustering solution of a circuit.  ...  Our algorithm SCPlace consistently outperforms the state-of-the-art FPGA placement flow (T-VPack + VPR) with an average reduction of up to 36% in total wirelength and 31% in longest path delay.  ...  Rpack [4] introduces an effective routability metric and presents a routability driven clustering algorithm for cluster-based FPGAs.  ... 
doi:10.1007/978-3-540-30117-2_18 fatcat:3cf4dcqi4bbuvd7junubjooz4q

Enhancing timing-driven FPGA placement for pipelined netlists

Ken Eguro, Scott Hauck
2008 Proceedings of the 45th annual conference on Design automation - DAC '08  
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs.  ...  In this paper we discuss some of the inherent quality and runtime issues pipelined netlists present to existing timingdriven placement approaches.  ...  Classical Timing-Driven Placement VPR [5] is one of the most popular academic FPGA place and route tool suites.  ... 
doi:10.1145/1391469.1391480 dblp:conf/dac/EguroH08 fatcat:po3ek3j4lfeo5p62h36xofmt3m

Scalable and deterministic timing-driven parallel placement for FPGAs

Chris C. Wang, Guy G.F. Lemieux
2011 Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '11  
This thesis describes a parallel implementation of the timing-driven VPR 5.0 simulated-annealing placement engine.  ...  The full timingdriven placement algorithm is parallelized, including swap evaluation, boundingbox calculation and the detailed timing-analysis updates.  ...  Clearly, timing-driven placement is highly beneficial for FPGA devices and the following section will give a brief introduction to the timing-analysis engine used in VPR.  ... 
doi:10.1145/1950413.1950445 dblp:conf/fpga/WangL11 fatcat:2xpnc3uhebclvftblpwskizlru

Fast timing-driven partitioning-based placement for island style FPGAs

Pongstorn Maidee, Cristinel Ababei, Kia Bazargan
2003 Proceedings of the 40th conference on Design automation - DAC '03  
In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization.  ...  An efficient terminal alignment heuristic for delay minimization is employed to further optimize the delay of the circuit in the routing phase.  ...  Timing driven placement for FPGAs can be classified into two main categories: net-based and path-based approaches.  ... 
doi:10.1145/775983.775984 fatcat:7t2m55w5w5ertotp4ovs5zzqqi

New timing and routability driven placement algorithms for FPGA synthesis

Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong
2007 Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07  
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead.  ...  CONCLUSIONS AND FUTURE WORK In this paper, we presented timing and congestion driven placement algorithms for FPGAs.  ...  Timing-Driven Approaches In placement, timing-driven algorithms can be broadly divided into two classes: path-based and net-based.  ... 
doi:10.1145/1228784.1228918 dblp:conf/glvlsi/ZhuoLZCH07 fatcat:mcrmixezungfbbzwhs53iufgdi

Fast timing-driven partitioning-based placement for island style FPGAs

Pongstorn Maidee, Cristinel Ababei, Kia Bazargan
2003 Proceedings of the 40th conference on Design automation - DAC '03  
In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization.  ...  An efficient terminal alignment heuristic for delay minimization is employed to further optimize the delay of the circuit in the routing phase.  ...  Timing driven placement for FPGAs can be classified into two main categories: net-based and path-based approaches.  ... 
doi:10.1145/775832.775984 dblp:conf/dac/MaideeAB03 fatcat:y4izd6l3efbjtmtt5jwvukbs34

Timing-driven placement for hierarchical programmable logic devices

Michael Hutton, Khosrow Adibsamii, Andrew Leaver
2001 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays - FPGA '01  
In this paper we discuss new techniques for timing-driven placement and adaptive delay computation for hierarchical PLD architectures.  ...  Our contributions include a specification of the overall TDC (timing-driven compilation) algorithm, an analysis of heuristics such as a variant of multi-start partitioning, a new method for adaptive delay  ...  [6] use simulated annealing as a tool for timing-driven placement. In the former, the target is standard-cell devices, in the latter the Triptych FPGA architecture.  ... 
doi:10.1145/360276.360286 fatcat:73dus3islzbnpjg6atftfofuu4

Fast timing-driven partitioning-based placement for island style FPGAs

P. Maidee, C. Ababei, K. Bazargan
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)  
In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization.  ...  An efficient terminal alignment heuristic for delay minimization is employed to further optimize the delay of the circuit in the routing phase.  ...  Timing driven placement for FPGAs can be classified into two main categories: net-based and path-based approaches.  ... 
doi:10.1109/dac.2003.1219089 fatcat:p2r6634hgbdvnpprtyenaa23yu

Timing driven placement reconfiguration for fault tolerance and yield enhancement in FPGAs

A. Mathur, C.L. Liu
Proceedings ED&TC European Design and Test Conference  
The concept of a slack neighborhood graph is used as a general tool for timing driven recon guration with a low increase in critical path delay.  ...  The primary objective of the placement recon guration is to minimize timing degradation.  ...  Timing Driven Reconguration In this section, we give a n o v erview of our algorithm for timing driven placement reconguration. Many of the details are omitted due to lack of space.  ... 
doi:10.1109/edtc.1996.494143 dblp:conf/date/MathurL96 fatcat:7iubffbdfbdsxbalbwatu3vvym

Area-speed tradeoffs for hierarchical field-programmable gate arrays

Vi Cuong Chan, David M. Lewis
1996 Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays - FPGA '96  
This paper investigates area-speed trade-offs for Hierarchical FPGA (HFPGA) architectures.  ...  Experiments were also performed to determine the effect of timing optimized placements on routing channel requirements.  ...  driven for FPGAs 2.16 156.1 timing driven for FPGAs 1.58 170.0  ... 
doi:10.1145/228370.228378 dblp:conf/fpga/ChanL96 fatcat:l6by44fbzvcmfcdf244czwfc5y

Soft error reliability aware placement and routing for FPGAs

Mohammed A. Abdul-Aziz, Mehdi B. Tahoori
2010 2010 IEEE International Test Conference  
Timing Driven placement routed using the Timing Driven router 17 Critical Path Timing for the Path Timing Driven placement routed using the Timing Driven router 18 Number of track (per channel) used for  ...  driven placement and 15.3% over the path timing driven placement. 1 Open Sensitive bits for the Path Timing Driven placement routed using the Timing Driven router 2 Open Sensitive bits for the Bounding  ... 
doi:10.1109/test.2010.5699279 dblp:conf/itc/Abdul-AzizT10 fatcat:val6q2abybhqnkgnl72zsyi67q

Dynamic FPGA routing for just-in-time FPGA compilation

Roman Lysecky, Frank Vahid, Sheldon X.-D. Tan
2004 Proceedings of the 41st annual conference on Design automation - DAC '04  
A JIT compiler for FPGAs requires the development of lean versions of technology mapping, placement, and routing algorithms, of which routing is the most computationally and memory expensive step.  ...  a hardware circuit for a single specific FPGA.  ...  We would also like to acknowledge Kees Vissers for his valuable input on developing JIT FPGA compilation.  ... 
doi:10.1145/996566.996819 dblp:conf/dac/LyseckyVT04 fatcat:5nmkokcyw5dejnudqxk3x32kzq

Performance Improvements through Timing Driven Reconfiguration of Black-Boxes in Platform FPGAs

Priya Sundararajan, Sridhar Krishnamurthy, N Vijaykrishnan, Kamal Chaudhary, Rajeev Jayaraman
2006 2006 IEEE International SOC Conference  
In this paper, we discuss a timing driven reconfiguration technique to improve performance of DSP designs on platform FPGAs by (i) Optimal register placement algorithms within the DSP48 block and (ii)  ...  Timing driven mechanism to have maximal pipeline depth.  ...  With the market looking towards platform FPGAs for system on chip solutions, our timing driving algorithm would play a crucial role in realizing the performance goals required for building such systems  ... 
doi:10.1109/socc.2006.283857 dblp:conf/socc/SundararajanKVCJ06 fatcat:phm3txro6vhvzmhfzmevpc4joa

Applications of slack neighborhood graphs to timing driven optimization problems in FPGAs

Anmol Mathur, K. C. Chen, C. L. Liu
1995 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays - FPGA '95  
in FPGAs and timing driven design re-engineering for FPGAs.  ...  In this paper we examine three dierent problems related to FPGA placement: timing driven placement of a technology mapped circuit, timing driven reconguration for yield enhancement and fault tolerance  ...  Timing Driven Placement Now w e briey outline our timing driven placement algorithm for FPGAs and show h o w the timing driven relocation problem is one of the major components of the algorithm.  ... 
doi:10.1145/201310.201329 dblp:conf/fpga/MathurCL95 fatcat:xvgz73nxszc4hcblxvimi5slxq
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