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Timing Analysis of an Avionics Case Study on Complex Hardware/Software Platforms

Franck Wartel, Leonidas Kosmidis, Adriana Gogonel, Andrea Baldovin, Zoe Stephenson, Benoit Triquet, Eduardo Quiñones, Code Lo, Enrico Mezzetti, Ian Broster, Jaume Abella, Liliana Cucu-Grosjean (+2 others)
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015   unpublished
Probabilistic Timing Analysis (PTA) in general and its measurement-based variant called MBPTA in particular have been shown to facilitate the estimation of the worst-case execution time (WCET).  ...  While solutions to those challenges have been proven on benchmarks, they have not been proven yet on real-world applications, whose timing analysis is far more challenging than that of simple benchmarks  ...  MBPTA has been successfully applied on an avionics case study run on a single-core processor equipped with the hardware support needed to enable the use of MBPTA [35] .  ... 
doi:10.7873/date.2015.0189 fatcat:ntjszsa37ndfneeitq7kg6rbj4

A Customizable Monitoring Infrastructure for Hardware/Software Embedded Systems [chapter]

Martial Chabot, Laurence Pierre
2014 Lecture Notes in Computer Science  
Experimental results on industrial case studies illustrate the benefits of the approach.  ...  In particular, due to the strong hardware/software interdependence, debugging the embedded software is a demanding task.  ...  Avionics Flight Control Remote Module This case study (from Airbus) is an avionics module dedicated to processing data from sensors and controlling actuators according to predefined flight laws.  ... 
doi:10.1007/978-3-662-44857-1_12 fatcat:ehkvuk74o5a2dc5jdhwdkfincq

A Hardware/Software Architecture for UAV Payload and Mission Control

Enric Pastor, Juan Lopez, Pablo Royo
2006 2006 ieee/aiaa 25TH Digital Avionics Systems Conference  
This paper presents an embedded hardware/software architecture specially designed to be applied on mini/micro Unmanned Aerial Vehicles (UAV).  ...  This type of UAV shares limitations with most computer embedded systems: limited space, limited power resources, increasing computation requirements, complexity of the applications, time to market requirements  ...  Conclusions This paper has introduced a hardware/software architecture designed to be used as avionics for mission and payload control in the area of Unmanned Aerial Vehicles.  ... 
doi:10.1109/dasc.2006.313738 fatcat:jkh7i3r3avddnfxde3ydpfkife

Hardware-software codesign of embedded systems

M. Chiodo, P. Giusto, A. Jurecska, H.C. Hsieh, A. Sangiovanni-Vincentelli, L. Lavagno
1994 IEEE Micro  
Creating an embedded computer system which meets its performance, cost, and design time goals is a hardware-software co-design p r o b l e w h e design of the hardware and software components influence  ...  We describe analysis techniques for hardware and software relevant to the architectural choices required for hardware-software co-design.  ...  time of the hardware-software system.  ... 
doi:10.1109/40.296155 fatcat:ry7g2gcfkvdo3fnmi73knppf5a

Hardware-software co-design of embedded systems

W.H. Wolf
1994 Proceedings of the IEEE  
Creating an embedded computer system which meets its performance, cost, and design time goals is a hardware-software co-design p r o b l e w h e design of the hardware and software components influence  ...  We describe analysis techniques for hardware and software relevant to the architectural choices required for hardware-software co-design.  ...  time of the hardware-software system.  ... 
doi:10.1109/5.293155 fatcat:jytgx6etfnhbpfz5zqxbv6oiua

Control/Architecture Codesign for Cyber-Physical Systems [chapter]

Wanli Chang, Licong Zhang, Debayan Roy, Samarjit Chakraborty
2016 Handbook of Hardware/Software Codesign  
With the increasing size and complexity of such systems, the resource awareness in the system design is becoming an important issue.  ...  Control/architecture codesign methods integrate the design of controllers and the design of embedded platforms to exploit the characteristics on both sides.  ...  The time complexity of PSO is clearly polynomial.  ... 
doi:10.1007/978-94-017-7358-4_37-1 fatcat:j3jhedirjjgzjp3zeh3bi4yiai

Model Checking Memory-Related Properties of Hardware/Software Co-designs [chapter]

Marcel Pockrandt, Paula Herber, Verena Klös, Sabine Glesner
2013 IFIP Advances in Information and Communication Technology  
We demonstrate both, the verification performance and the errordetection capabilities of our approach with experimental results from various case studies, including an industrial SystemC/TLM design of  ...  Hardware/software codesign enables the integrated development of hardware and software in a single design language.  ...  We used three models of different complexity, including an industrial case study of the AMBA advanced high performance bus.  ... 
doi:10.1007/978-3-642-38853-8_9 fatcat:mhkrcphbmvbt7j5kpzecabfi7u

Symbolic voter placement for dependability-aware system synthesis

Felix Reimann, Michael Glaβ, Martin Lukasiewycz, Joachim Keinert, Christian Haubelt, Jürgen Teich
2008 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis - CODES/ISSS '08  
and safety, respectively, 2) an efficient dependability analysis approach to evaluate lifetime reliability and safety, and 3) results from synthesizing a Motion-JPEG decoder for an FPGA platform using  ...  As a result, a set of high-quality solutions of the decoder with maximized reliability, safety, performance, and simultaneously minimized resource requirements is achieved.  ...  The definitive version was published in Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, ( In this paper, we propose a new dependability  ... 
doi:10.1145/1450135.1450190 dblp:conf/codes/ReimannGLKHT08 fatcat:zppgzvubsfgq5jptpvrpezvqb4

Scratchpad allocation for concurrent embedded software

Vivy Suhendra, Abhik Roychoudhury, Tulika Mitra
2008 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis - CODES/ISSS '08  
Our goal is to optimize the worst-case response time (WCRT) of the application through runtime reloading of the scratchpad memory content at appropriate execution points.  ...  We evaluate our memory allocation scheme on two real-world embedded applications controlling an Unmanned Aerial Vehicle (UAV) and an in-orbit monitoring instrument, respectively.  ...  ACKNOWLEDGMENTS This work was partially supported by NUS research project "Platform-aware Timing Analysis of Behavioral System Models" (R252-000-321-112).  ... 
doi:10.1145/1450135.1450145 dblp:conf/codes/SuhendraRM08 fatcat:lwtvzwnub5esfdk7frb3n5jkbi

Worst-case throughput analysis of real-time dynamic streaming applications

Firew Siyoum, Marc Geilen, Orlando Moreira, Henk Corporaal
2012 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '12  
The case studies demonstrate the benefits of capturing intra-application dynamism through SADF for tighter temporal analysis.  ...  The investigation conducts case studies on different applications, such as LTE, which is a recent cellular connectivity standard, and MPEG4 video decoder.  ...  case-study applications of this chapter.  ... 
doi:10.1145/2380445.2380517 dblp:conf/codes/SiyoumGMC12 fatcat:2vxjwmsjfvaf3dnfsm4k4dmwra

ePAPI: Performance Application Programming Interface for Embedded Platforms

Jeremy Giesen, Enrico Mezzetti, Jaume Abella, Enrique Fernández, Francisco J. Cazorla, Michael Wagner
2019 Worst-Case Execution Time Analysis  
PMCs are increasingly considered in embedded time-critical domains to collect in-depth information, e.g. cache misses and memory accesses, of software execution time on complex multicore platforms.  ...  In this paper, we address the need for a standardized PMC interface in the embedded domain, especially in view to support timing characterization of embedded platforms.  ...  Overall, PMCs and Performance Monitoring Units (PMUs) in general, are instrumental to timing analysis on complex COTS high-performance hardware platforms.  ... 
doi:10.4230/oasics.wcet.2019.3 dblp:conf/wcet/GiesenMAFC19 fatcat:shdluelgzffozoo246645t33va

D4.1: Software System Specification for Trustworthy and Secure Computing Platforms

UOP, KIT, VECTOR, QUB, FENTISS
2021 Zenodo  
The first part of this deliverable describes the two main components of the XANDAR run-time engine, the XtratuM hypervisor of FENTISS and the AUTOSAR adaptive API, and their adoption to the XANDAR platform  ...  The goal of Task 4.1 is to specify the main components of the XANDAR software platform and the respective run-time system that will enable the online monitoring, self-adaptation and self-healing mechanisms  ...  An example of a trigger condition is the situation in which an ML/AI item violates its Operational Design Domain (ODD) as described for the avionics use case in D1.1.  ... 
doi:10.5281/zenodo.6539496 fatcat:dhlzvvtsn5bhzesaktegc7w2eu

Securing Vehicle-to-Everything (V2X) Communication Platforms

Monowar Hasan, Sibin Mohan, Takayuki Shimizu, Hongsheng Lu
2020 IEEE Transactions on Intelligent Vehicles  
In this survey, we provide an extensive overview of V2X ecosystem.  ...  Modern vehicular wireless technology enables vehicles to exchange information at any time, from any place, to any network-forms the vehicle-to-everything (V2X) communication platforms.  ...  ) [153] , [154] ; (iii) hardware/software architecture for over-the-air (OTA) updates [155] ; (iv) statistical analysis of ECU firmware images by reverse engineering to detect misbehaving ECUs [156  ... 
doi:10.1109/tiv.2020.2987430 fatcat:egw4hik2onfarc6nsjsng2r6ei

Virtual execution platforms for mixed-time-criticality systems

Kees Goossens, Ashkan Beyranvand Nejad, Andrew Nelson, Shubhendu Sinha, Arnaldo Azevedo, Karthik Chandrasekar, Manil Dev Gomony, Sven Goossens, Martijn Koedam, Yonghui Li, Davit Mirzoyan, Anca Molnos
2013 ACM SIGBED Review  
Moreover, three new case studies illustrate all claimed benefits: 1) An example firm-realtime CSDF H.263 decoder is automatically mapped and verified. 2) Applications with different models of computation  ...  Mapping and analysis of KPN and TT applications is not automated but they do run composably in their allocated virtual platforms.  ...  CASE STUDIES This section contains three case studies illustrating: 1) automatically mapping a FRT CSDF application on a platform instance, using formal performance analysis; 2) running applications with  ... 
doi:10.1145/2544350.2544353 fatcat:lxmodfh25jdrpifqc727rnuija

The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

Kim Grüttner, Philipp A. Hartmann, Kai Hylla, Sven Rosinger, Wolfgang Nebel, Fernando Herrera, Eugenio Villar, Carlo Brandolese, William Fornaciari, Gianluca Palermo, Chantal Ykman-Couvreur, Davide Quaglia (+2 others)
2013 Microprocessors and microsystems  
We propose an efficient code annotation technique for timing and power properties enabling fast host execution as well as adaptive collection of power traces.  ...  Combined with a flexible design-space exploration (DSE) approach our flow allows a trade-off analysis between different platforms, mapping alternatives, and optimization techniques, based on domain-specific  ...  Acknowledgment The authors thank all partners involved in the COMPLEX FP7 European Integrated Project [6] , funded by the European Commission under Grant Agreement 247999.  ... 
doi:10.1016/j.micpro.2013.09.001 fatcat:7a5ycc45m5h7nkjhxhe4u2j7am
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