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Joint Watermarking for Image Reliability Control in Encrypted and Compressed Domains

Miss. Ishwari Pund
2021 International Journal for Research in Applied Science and Engineering Technology  
In a first time, it permits the admittance to watermarking-based security administrations from the scrambled and the compacted bitstreams without parsing them even part of the way.  ...  It gets conceivable to follow images and control their dependability from both the encoded and compacted spaces.  ...  Figure 1 : 1 Shows file size on x axis and Encryption Time on Y-axis 2 ) Results 2 :Figure 2 : 222 Shows file size on x axis and Decryption Time on Y-axis Shows file size on x axis and Decryption Time  ... 
doi:10.22214/ijraset.2021.37022 fatcat:cmoudeetcnaapkvtz3piwclywi

Abstracts of Current Computer Literature

1970 IEEE transactions on computers  
Secondly, the exact minimum distance of a subclass of BCH codes is established and a tight BCH bound on the minimum distance of the dual of a polynomial code is obtained.  ...  It is hoped that these properties may impart more algebraic structure to BCH codes and geometry codes.  ... 
doi:10.1109/t-c.1970.222892 fatcat:tpn743oi6za4dfhaudkprjabmm

FPGA-based design of an evolutionary controller for collision-free robot navigation

M. A. H. B. Azhar, K. R. Dimond
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
access (CDMA) systems the base station identifies each user in a cell by unique orthogonal (Walsh) codes.  ...  Experimental results are reported with the AccelFPGA compiler on a set of 8 MATLAB benchmarks that are mapped onto the Xilinx Virtex II and Altera Stratix FPGAs.  ...  Effective search methods are exploited in order to minimize the number of test configurations and the total diagnosis time.  ... 
doi:10.1145/611817.611852 dblp:conf/fpga/AzharD03 fatcat:juups7gn3ve2vhw2fbicwvt5kq

Lattice adaptive filter implementation for FPGA

Zdenek Pohl, Rudolf Matoušek, Jirí Kadlec, Milan Tichý, Miroslav Lícko
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
access (CDMA) systems the base station identifies each user in a cell by unique orthogonal (Walsh) codes.  ...  Experimental results are reported with the AccelFPGA compiler on a set of 8 MATLAB benchmarks that are mapped onto the Xilinx Virtex II and Altera Stratix FPGAs.  ...  Effective search methods are exploited in order to minimize the number of test configurations and the total diagnosis time.  ... 
doi:10.1145/611817.611877 dblp:conf/fpga/PohlMKTL03 fatcat:vg523unfzvcmvl2rsw4ja3ksma

Reduction and decomposition of differential automata: Theory and applications [chapter]

Alexey S. Matveev, Andrey V. Savkin
1998 Lecture Notes in Computer Science  
First and Second order Reed-Mueller codes, t-designs, steiner systems. Weight distribution of codes. Generalized BCH codes. Self dual codes and invariant theory.  ...  Connectedness and Compactness: Connected spaces, Connected subspaces of the real line, Components and local connectedness, Compact spaces, Heine-Borel Theorem, Local -compactness.  ... 
doi:10.1007/3-540-64358-3_48 fatcat:hqwvar3zbfftdhg4cybpjwogde

2018 IndexIEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 26

2018 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Hsu, K., Chen, Y., Lee, Y., and Chang, S., Contactless Testing for Prebond Interposers; TVLSI June 2018 1005-1014 Hsu, Y., see Liu, Z., 1565-1574 Hu, J., see Wang, Y., TVLSI May 2018 805-817 Hu, J  ...  ., see 2723-2736 , VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems; TVLSI Feb. 2018 262-271 Hsieh, Y., see Tsai, Y., TVLSI May 2018 945-957  ...  ., +, TVLSI April 2018 792-802 BCH codes Design and Analysis of Energy-Efficient and Reliable 3-D ReRAM Cross- Point Array System.  ... 
doi:10.1109/tvlsi.2019.2892312 fatcat:rxiz5duc6jhdzjo4ybcxdajtbq

A Blockchain Based System for Healthcare Digital Twin

Sadman Sakib Akash, Md Sadek Ferdous
2022 IEEE Access  
Then, we have used the patient centric mathematical data model to formally define the semantic and scope of our proposed Healthcare Digital Twin (HDT ) system based on Blockchain.  ...  Digital Twin (DT) is an emerging technology that replicates any physical phenomenon from a physical space to a digital space in congruence with the physical state.  ...  In terms of Digital Twin, where data will be perceived from physical space in real time and, concurrently the analyzing, processing, and decision making, will be done in virtual space [67] , there will  ... 
doi:10.1109/access.2022.3173617 fatcat:5wwuhlgbs5huxi2liralnjmrsy

Methods for fault tolerance in networks-on-chip

Martin Radetzki, Chaochao Feng, Xueqian Zhao, Axel Jantsch
2013 ACM Computing Surveys  
The article at hand reviews the failure mechanisms, fault models, diagnosis techniques, and fault-tolerance methods in on-chip networks, and surveys and summarizes the research of the last ten years.  ...  Research on fault-tolerant Networks-on-Chip tries to mitigate partial failure and its effect on network performance and reliability by exploiting various forms of redundancy at the suitable network layers  ...  BIST-based error detection generally comprises the Test Data Generator (TDG) and the Test Response Analyzer (TRA) in the switch.  ... 
doi:10.1145/2522968.2522976 fatcat:3t4b3rhbgbc2bphjevpkzlpm6u

A multi-level view of dependable computing

Behrooz Parhami
1994 Computers & electrical engineering  
Erroneous information or states may or may not cause the affected subsystem to malfunction, depending on the subsystem's design and error tolerance.  ...  Specifically, impairments to dependability are viewed from six levels, each being more abstract than the previous one.  ...  Research Council of Canada under Grant Nos Gll40 and A5515.  ... 
doi:10.1016/0045-7906(94)90048-5 fatcat:q3fwsc6eivab3l47wx6vtv6vtq

iLogDemons: A Demons-Based Registration Algorithm for Tracking Incompressible Elastic Biological Tissues

Tommaso Mansi, Xavier Pennec, Maxime Sermesant, Hervé Delingette, Nicholas Ayache
2010 International Journal of Computer Vision  
Building on this result, we replace the Gaussian smoothing by an efficient elastic-like regulariser based on isotropic differential quadratic forms of vector fields.  ...  Tests on synthetic incompressible deformations showed that our approach outperforms the original logDemons in terms of elastic incompressible deformation recovery without reducing the image matching accuracy  ...  The pseudo-code of the algorithm is: A Time-Integration of Stationary Velocity Fields Algorithm 3 Scaling-and-Squaring Algorithm Require: Velocity field v 1: Choose n such that v/2 n ≤ 0.5 2: Explicit  ... 
doi:10.1007/s11263-010-0405-z fatcat:5zxwztuxe5ah5ek4umxw2wvvwq

Abstracts of Current Computer Literature

1971 IEEE transactions on computers  
The performance calculations are based on the use of BCH codes for error detection and correction up to the full correction capability of the code.  ...  RM-6248-PR, 14 pp., March 1970; CFSTI, AD 704 568, $3.00. 8233 Space / Space Time Trade-Offs in Hash Coding with Allowabe Errors, B. H. Bloom (Computer Usage Co., Newton Upper Falls); Comm.  ... 
doi:10.1109/t-c.1971.223093 fatcat:xxhdbzhhdzdp5e5wznkfj3yoai

2018 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 65

2018 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
., and Pandey, N  ...  Lyu, W., +, TCSI June 2018 1954-1967 BCH codes Advanced Bit Flip Concatenates BCH Code Demonstrates 0.93% Cor- rectable BER and Faster Decoding on (36 864, 32 768) Emerging Memories.  ...  Test on Wafer Level for a MEM Gyroscope Readout Based on ∆Σ Modulation.  ... 
doi:10.1109/tcsi.2019.2896877 fatcat:3lzpngw2ofdjhiculf7ehrjeam

2019 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 66

2019 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Accurate and Fast On-Wafer Test Circuitry for Device Array Characterization in Wafer Acceptance Test.  ...  ., +, TCSI Jan. 2019 175-188 Life testing Accurate and Fast On-Wafer Test Circuitry for Device Array Characterization in Wafer Acceptance Test.  ... 
doi:10.1109/tcsi.2020.2966967 fatcat:f663jj5g45e3peggn3gwn5jys4

Application of Saluja-Karpovsky compactors to test responses with many unknowns

J.H. Patel, S.S. Lumetta, S.M. Reddy
Proceedings. 21st VLSI Test Symposium, 2003.  
This paper addresses the problem of compacting test responses in the presence of unknowns at the input of the compactor by exploiting the capabilities of well-known error detection and correction codes  ...  Use of non-proprietary codes found in the literature of 1950s; and 6. Independent of the circuit and the test generator.  ...  We also thank Subhasish Mitra and Kee Sup Kim of Intel Corp. for their paper at the ITC, which inspired us to work on this problem.  ... 
doi:10.1109/vtest.2003.1197640 dblp:conf/vts/PatelLR03 fatcat:omi3ie6jl5bwbmmhvrtc4sw67u

Program

2021 2021 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW)  
Recently, a new subclass of BCH codes was proposed and called quasi-reversible BCH codes.  ...  Based on the influence of different types of urban space, time, and industry categories, pedestrians will create different space use patterns.  ... 
doi:10.1109/icce-tw52618.2021.9602919 fatcat:aetmvxb7hfah7iuucbamos2wgu
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