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2018 IndexIEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 26

2018 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Hsu, K., Chen, Y., Lee, Y., and Chang, S., Contactless Testing for Prebond Interposers; TVLSI June 2018 1005-1014 Hsu, Y., see Liu, Z., 1565-1574 Hu, J., see Wang, Y., TVLSI May 2018 805-817 Hu, J  ...  ., see 2723-2736 , VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems; TVLSI Feb. 2018 262-271 Hsieh, Y., see Tsai, Y., TVLSI May 2018 945-957  ...  ., +, Leakage Power Attack-Resilient Symmetrical 8T SRAM Cell. Giterman, R., +, TVLSI Oct. 2018 2180-2184 Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test.  ... 
doi:10.1109/tvlsi.2019.2892312 fatcat:rxiz5duc6jhdzjo4ybcxdajtbq

Device and Circuit Architectures for In‐Memory Computing

Daniele Ielmini, Giacomo Pedretti
2020 Advanced Intelligent Systems  
In-memory computing (IMC) appears as a promising approach to suppress the memory bottleneck and enable higher parallelism of data processing, thanks to the memory array architecture.  ...  Finally, array architectures for computing are reviewed, including typical architectures for neural network accelerators, content addressable memory (CAM), and novel circuit topologies for general-purpose  ...  Acknowledgements This article has received funding from the European Research Council (ERC) under the European Union's Horizon 2020 research and innovation program (grant agreement no. 648635).  ... 
doi:10.1002/aisy.202000040 fatcat:qo4yfcftdva2npkdltopwgqkby

Recent progress in analog memory-based accelerators for deep learning

Hsinyu Tsai, Stefano Ambrogio, Pritish Narayanan, Robert M Shelby, Geoffrey W Burr
2018 Journal of Physics D: Applied Physics  
We survey recent progress in the use of analog memory devices to build neuromorphic hardware accelerators for deep learning applications.  ...  We discuss how the strengths and weaknesses of analog memory-based accelerators match well to the weaknesses and strengths of digital accelerators, and attempt to identify where the future hardware opportunities  ...  They also demonstrate resilience to drift (in measured NN performance), over a timescale of 7 months, and temperature invariance.  ... 
doi:10.1088/1361-6463/aac8a5 fatcat:2xxoiiv3a5fj5hxjoamsndl66a

Memristors: Devices, Models, and Applications [Scanning the Issue]

Pinaki Mazumder, Sung Mo Kang, Rainer Waser
2012 Proceedings of the IEEE  
Ebong for his assistance in searching the database of memristor papers, cataloging the applications of memristors, and writing the last section of this article. published  ...  Acknowledgment The authors would like to thank I.  ...  From a research perspective, some papers focus on how unit cells would work: for example, STDP in [1] , associative memory demonstration [2] , and a feedback write scheme for a memristive memory in  ... 
doi:10.1109/jproc.2012.2190812 fatcat:n7ux4tc64bd6bcncqovjq3igli

2021 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 40

2021 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name.  ...  The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination.  ...  ., +, TCAD Jan. 2021 66-77 Exploiting Process Variations to Secure Photonic NoC Architectures From Multilevel Dataflow-Driven Macro Placement Guided by RTL Structure and TCAD Jan. 2021 24-37 Integrated  ... 
doi:10.1109/tcad.2021.3136047 fatcat:ppooj4g65nc2zonj7szclerc2y

Phase Change and Magnetic Memories for Solid-State Drive Applications

Cristian Zambelli, Gabriele Navarro, Veronique Sousa, Ioan Lucian Prejbeanu, Luca Perniola
2017 Proceedings of the IEEE  
However, due to the increased request for storage density coupled with performance that positions the storage tier closer to the latency of the processing elements, NAND Flash are becoming a serious bottleneck  ...  The state-of-the-art Solid State Drives now heterogeneously integrate NAND Flash and DRAM memories to partially hide the limitation of the non-volatile memory technology.  ...  For integration in the SCM context, one of most sought features is the possibility to act either on single cell domains (i.e., bit-alterability) as for DRAM or over an entire block of cells similar to  ... 
doi:10.1109/jproc.2017.2710217 fatcat:fof3pr2ixjfqdd3f226s4qqh7e

STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks

Thi-Nhan Pham, Quang-Kien Trinh, Ik-Joon Chang, Massimo Alioto
2022 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
To suppress the need for a standalone and accurate voltage reference, the time-based sensing (TBS) technique in [21] is adopted to move read-out from voltage to time domain.  ...  The effect of temperature variations on the inference accuracy is depicted in Fig. 13 for N=128.  ... 
doi:10.1109/jetcas.2022.3169759 fatcat:2632kjqhi5ar7etmg2fhe2tq5e

Dependable embedded systems

2008 2008 6th IEEE International Conference on Industrial Informatics  
This Series addresses current and future challenges pertaining to embedded hardware, software, specifications and techniques.  ...  Titles in the Series cover a focused set of embedded topics relating to traditional computing devices as well as hightech appliances used in newer, personal devices, and related topics.  ...  We would like to thank Arun Subramaniyan, Duo Sun and Segnon Jean Bruno Ahandagbe for their contributions to parts of the works cited in this chapter.  ... 
doi:10.1109/indin.2008.4618103 fatcat:hal6brsgsjg5rlo3u5xil46pxi

Eurolab-4-HPC Long-Term Vision on High-Performance Computing [article]

Theo Ungerer, Paul Carpenter
2018 arXiv   pre-print
The US IEEE society wants to "reboot computing" and the HiPEAC Vision 2017 sees the time to "re-invent computing", both by challenging its basic assumptions.  ...  The objective of the Eurolab-4-HPC vision is to provide a long-term roadmap from 2023 to 2030 for High-Performance Computing (HPC).  ...  RRAM can deliver 100x lower read latency and 20x faster write performance compared to NAND Flash [12] . CBRAM can also write with relatively low energy and with high speed.  ... 
arXiv:1807.04521v1 fatcat:5neetrgubjhnvcajcktpkohrzq

2020 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 39

2020 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
., +, TCAD April 2020 946-951 Finite difference time-domain analysis Fast Methodology for Time-Domain Analysis of Nonlinear-Loaded Trans- mission Line Excited by an Arbitrary Modulated Signal.  ...  -1687 Error Diluting: Exploiting 3-D nand Flash Process Variation for Efficient Read on LDPC-Based SSDs.  ...  Entropy-Directed Scheduling for FPGA High-Level Synthesis. Shen, M., +, TCAD Oct. 2020 2588 -2601 FLASH: Fast, Parallel, and Accurate Simulator for HLS.  ... 
doi:10.1109/tcad.2021.3054536 fatcat:wsw3olpxzbeclenhex3f73qlw4

2020 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 67

2020 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Yang, J., +, TCSI Dec. 2020 5550-5560 An Architecture for Real-Time Arbitrary and Variable Sampling Rate Conversion With Application to the Processing of Harmonic Signals.  ...  ., +, TCSI Dec. 2020 4360-4369 Filtering theory An Architecture for Real-Time Arbitrary and Variable Sampling Rate Con- version With Application to the Processing of Harmonic Signals.  ...  Lin, Y., +, TCSI Feb. 2020 634-646 Histograms Linearity Theory of Stochastic Phase-Interpolation Time-to-Digital Converter. Gammoh, K., +,  ... 
doi:10.1109/tcsi.2021.3055003 fatcat:kbmst5td2bbvtl7vpbj3knnkri

A Survey of Near-Data Processing Architectures for Neural Networks [article]

Mehdi Hassanpour, Marc Riera, Antonio González
2021 arXiv   pre-print
Finally, we discuss open challenges and future perspectives that need to be explored in order to improve and extend the adoption of NDP architectures for future computing platforms.  ...  In this paper, we present a survey of techniques for designing NDP architectures for NN.  ...  Liu, and rrams to extend analog dataflow in an end-to-end in-memory processing Y.  ... 
arXiv:2112.12630v1 fatcat:drkwrztkazd3hlblxc7i4kgn2a

2018 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 65

2018 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
., and Pandey, N  ...  ., +, TCSI Aug. 2018 2389-2402 A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits.  ...  ., +, TCSI Nov. 2018 3639-3650 A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits.  ... 
doi:10.1109/tcsi.2019.2896877 fatcat:3lzpngw2ofdjhiculf7ehrjeam

2022 Roadmap on Neuromorphic Computing and Engineering [article]

Dennis V. Christensen, Regina Dittmann, Bernabé Linares-Barranco, Abu Sebastian, Manuel Le Gallo, Andrea Redaelli, Stefan Slesazeck, Thomas Mikolajick, Sabina Spiga, Stephan Menzel, Ilia Valov, Gianluca Milano (+47 others)
2022 arXiv   pre-print
In the Von Neumann architecture, processing and memory units are implemented as separate blocks interchanging data intensively and continuously.  ...  This new generation of computers has the potential to be used for the storage and processing of large amounts of digital information with much lower power consumption than conventional processors.  ...  Concluding Remarks Integrating event-based vision sensing and processing with neuromorphic computation techniques is expected to yield solutions that will be able to penetrate the artificial vision market  ... 
arXiv:2105.05956v3 fatcat:pqir5infojfpvdzdwgmwdhsdi4

2020 Index IEEE Transactions on Electron Devices Vol. 67

2020 IEEE Transactions on Electron Devices  
Temperature Instability Degradation Regimes in Full {V G , V D } Bias Space: Implications and Peculiarities; TED Aug. 2020 3315-3322 Jegadheesan, V., Sivasankaran, K., and Konar, A., Optimized Substrate  ...  , Y.S., Modeling of Current Mismatch and 1/f Noise for Halo-Implanted Drain-Extended MOSFETs; 4794-4801 Gupta, C., Gupta, A., Tuli, S., Bury, E., Parvais, B., and Dixit, A., Character-ization and Modeling  ...  ., +, TED June 2020 2329- 2335 Investigation of Read Disturb and Bipolar Read Scheme on Multilevel RRAM-Based Deep Learning Inference Engine.  ... 
doi:10.1109/ted.2021.3054448 fatcat:r4ertn5jordkfjjvorvss7n6ju
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