88 Hits in 7.3 sec

Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms

Mohammad H. Foroozannejad, Matin Hashemi, Alireza Mahini, Bevan M. Baas, Soheil Ghiasi
2014 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
network on chip-based task mapper through which, we underscore the unique requirements of task mapping for circuit-switched GALS architectures.  ...  We study the problem of mapping concurrent tasks of an application to cores of a chip multiprocessor that utilize circuit-switched interconnect and global asynchronous local synchronous (GALS) clocking  ...  of a packet-switched GALS architecture demonstrate the effectiveness of our approach in solving the mapping problem for GALS platforms.  ... 
doi:10.1109/tcad.2014.2299958 fatcat:c7mz2ca4lbb3vbrd4ortus64ie

Network-on-chip architectures and design methods

L. Benini, D. Bertozzi
2005 IEE Proceedings - Computers and digital Techniques  
performance and robust infrastructure for on-chip communication.  ...  In the long run, more aggressive solutions are needed to overcome the scalability limitation, and networks-on-chip (NoCs) are currently viewed as a 'revolutionary' approach to provide a scalable, high  ...  In time division circuit switching, bandwidth is shared by time division multiplexing connections over circuits.  ... 
doi:10.1049/ip-cdt:20045100 fatcat:y4mpq4dhvfe7tk3t4chf5j7se4

Distributed minimum energy point tracking for systems-on-chip

Cristinel Ababei, Chandana Tamma
2014 IEEE International Conference on Electro/Information Technology  
We propose a new design approach for systems-onchip. The goal of the proposed design approach is to minimize the overall energy consumption dynamically, during runtime.  ...  Applications can be mapped on this hardware platform such that energy consumption is minimized while system performance meets the desired target.  ...  DISCUSSION AND OPEN PROBLEMS Because the design approach proposed in this paper builds on the GALS philosophy, the resulting SoC platform bene- fits from inherent properties already known for the globally  ... 
doi:10.1109/eit.2014.6871770 dblp:conf/eit/AbabeiT14 fatcat:mfyaqenthrccdmzf2x526kf6au

Reconfigurable Multiprocessor Systems: A Review

Taho Dorta, Jaime Jiménez, José Luis Martín, Unai Bidarte, Armando Astarloa
2010 International Journal of Reconfigurable Computing  
Modern digital systems demand increasing electronic resources, so the multiprocessor platforms are a suitable solution for them.  ...  Flexibility is one of the strong points of this kind of system, and multiprocessor systems can even be reconfigured at run time, allowing hardware to be adjusted to the demands of the application.  ...  Acknowledgments This work has been supported by the Department of Education, Universities and Research of the Basque Government within the fund for research groups of the Basque university system IT394  ... 
doi:10.1155/2010/570279 fatcat:uho74omrjzbjhe5nwm36zupxam

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

Radu Marculescu, Umit Y. Ogras, Li-Shiuan Peh, Natalie Enright Jerger, Yatin Hoskote
2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Index Terms-Energy and power consumption, multiprocessor systems-on-chip (MPSoCs), networks-on-chip (NoCs), on-chip communication.  ...  Motivation, problem description, proposed approaches, and open issues are discussed for each problem from system, microarchitecture, and circuit perspectives.  ...  Marculescu of Carnegie Mellon University for the valuable feedback in the early stages of the manuscript.  ... 
doi:10.1109/tcad.2008.2010691 fatcat:2doy6ne6ybeptgy2avgvzjloji

Performance evaluation of Butterfly on-Chip Network for MPSoCs

Mohammad Arjomand, Hamid Sarbazi-Azad
2008 2008 International SoC Design Conference  
By Technology improvement, tens or hundreds of IP cores, operating complex functions with different frequencies, are mapped on-chip.  ...  This results in heterogeneous Multiprocessor System-on-Chip (MPSoC). The most MPSoC design challenges are due to infrastructure interconnect.  ...  So for optimal mapping of an application on chip, they scarcely provide any choice such that latency or power constraints are satisfied [6] .  ... 
doi:10.1109/socdc.2008.4815631 fatcat:zlxshmmbu5chtlmdhe2k3heimy

Towards a Modular RISC-V based Many-Core Architecture for FPGA Accelerators

Ahmed Kamaleldin, Salma Hesham, Diana Gohringer
2020 IEEE Access  
Moreover, the current trends toward open-source hardware frameworks are aimed to reduce design time and cost for complex system-on-chip architectures.  ...  Multi-/Many-core architectures are emerging as scalable, high-performance and energy-efficient computing platforms suitable for a variety of application domains from edge to cloud computing.  ...  Her research interests include reconfigurable computing, multiprocessor systems-on-chip (MPSoCs), networks-on-chip, simulators/virtual platforms, hardware-softwarecodesign and runtime systems.  ... 
doi:10.1109/access.2020.3015706 fatcat:zwknt4ke3nhvbgjdsh4ppoi4xu

FPGA and ASIC convergence

C. Valderrama, L. Jojczyk, P. DaCunha Possa, J. Dondo Gazzano
2011 2011 VII Southern Conference on Programmable Logic (SPL)  
However, state-of-the-art onchip bus topologies and protocols suffer from power, performance and scalability limitations [7] [8] .  ...  That motivated a design paradigm shift towards on-chip communication. Transaction Level Modeling (TLM) appeared to improve modeling and design efficiency of a communication scheme [6] .  ...  The MPPA provides scalability to processing power and real-time data flow for streaming media applications with hard real-time requirements [42] .  ... 
doi:10.1109/spl.2011.5782660 fatcat:tuym2sakgbhyxmkwjbj6tzfaqq

KTS: a real-time mapping algorithm for NoC-based many-cores

Audrey Queudet, Nadine Abdallah, Maryline Chetto
2017 Journal of Supercomputing  
Many-core architectures based on network-on-chip (NoC) are scalable and have the ability to meet the increasing performance requirements of complex concurrent applications (real-time video, communications  ...  This paper addresses the mapping problem of hard real-time task sets on NoC-based many-core processors. Our main contribution is a novel static mapping scheme called K-level task splitting (KTS).  ...  a summary of mapping approaches for multiprocessor systems.  ... 
doi:10.1007/s11227-017-1962-5 fatcat:xal5duyl7rao7ch4tqonccpvi4

Providing QoS Guarantees in a NoC by Virtual Channel Reservation [chapter]

Nikolay Kavaldjiev, Gerard J. M. Smit, Pascal T. Wolkotte, Pierre G. Jansen
2006 Lecture Notes in Computer Science  
Virtual channel reservation is a simple approach for providing guaranteed throughput services in a virtual channel network-on-chip.  ...  Introduction Multiprocessor System-on-Chip (MPSoC) is an emerging platform for the future mobile devices, e.g. PDAs, media players, mobile phones etc.  ...  The time for establishing a circuit cannot be neglected because all the switches along the circuit have to be reconfigured.  ... 
doi:10.1007/11802839_38 fatcat:fhqwrxe4pvc3tgzgu4bx4h3mhu

Energy-efficient Static Task Scheduling on VFI-based NoC-HMPSoCs for Intelligent Edge Devices in Cyber-physical Systems

Umair Ullah Tariq, Haider Ali, Lu Liu, John Panneerselvam, Xiaojun Zhai
2019 ACM Transactions on Intelligent Systems and Technology  
Network-on-Chip (NoC) based Multiprocessor System-on-Chip (MPSoC) architecture is becoming a de-facto computing platform for real-time applications due to its higher performance and Quality-of-Service  ...  The ever-growing demand for real-time applications has initiated to use Multiprocessor Systemon-Chips (MPSoCs) in modern embedded systems for CPS/WSN applications [2, 16, 44] .  ...  Consequently, Network-on-Chip (NoC) based Voltage Frequency Islands (VFIs), Globally Asynchronous Locally Synchronous (GALS) are widely adopted in large scale multiprocessor chip designs due to their higher  ... 
doi:10.1145/3336121 fatcat:glasc3fowzb75iliz7qbapejz4

NoC-Based Multiprocessor Architecture for Mixed-Time-Criticality Applications [chapter]

Kees Goossens, Martijn Koedam, Andrew Nelson, Shubhendu Sinha, Sven Goossens, Yonghui Li, Gabriela Breaban, Reinier van Kampenhout, Rasool Tavakoli, Juan Valencia, Hadi Ahmadi Balef, Benny Akesson (+4 others)
2017 Handbook of Hardware/Software Codesign  
After defining the concepts that such systems should follow, we described CompSOC, which is one example of a mixed-time-criticality platform.  ...  In this chapter we define what a mixed-time-criticality system is and what its requirements are.  ...  The NoC thus implements the GALS paradigm, which is essential for scalability (Concept 4).  ... 
doi:10.1007/978-94-017-7267-9_17 fatcat:sf5tvawf4ba2pbk4irvg4jhsim

HERMES: an infrastructure for low area overhead packet-switching networks on chip

Fernando Moraes, Ney Calazans, Aline Mello, Leandro Möller, Luciano Ost
2004 Integration  
The increasing complexity of integrated circuits drives the research of new on-chip interconnection architectures.  ...  A network on chip draws on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way.  ...  This multiprocessor NoC platform is presently used to execute parallel programs, such as sorting algorithms [46] .  ... 
doi:10.1016/j.vlsi.2004.03.003 fatcat:qmjv26gh3nh6zk76xr22d3wvkq

FLUX interconnection networks on demand

Stamatis Vassiliadis, Ioannis Sourdis
2007 Journal of systems architecture  
Our results clearly show that, based on the underlying network, different mappings are suitable for different algorithms.  ...  We experiment on several case studies, evaluate different algorithms, developed for meshes or trees, and map them on "grid"-like or reconfigurable physical interconnection networks.  ...  While multiprocessors can be implemented on a chip the VLSI design of single chip massive multiprocessors is only one of the challenges and by no means the only one.  ... 
doi:10.1016/j.sysarc.2007.01.006 fatcat:bdeixb2scngb7gzp3ccek3egm4

Energy-aware Scheduling of Streaming Applications on Edge-devices in IoT based Healthcare

Umair Ullah Tariq, Haider Ali, Lu Liu, James Hardy, Muhammad Kazim, Waqar Ahmed
2021 IEEE Transactions on Green Communications and Networking  
DVFS for real-time streaming applications.  ...  The reliance on Network-on-Chip (NoC) based Multiprocessor Systems-on-Chips (MPSoCs) is proliferating in modern embedded systems to satisfy the higher performance requirement of multimedia streaming applications  ...  Consequently, Multiprocessor System-on-Chips (MPSoCs) have become an essential element of the modern embedded systems for real-time multimedia data processing due to their higher performance, reliability  ... 
doi:10.1109/tgcn.2021.3056479 fatcat:ehf6cit4uvgo5adeuq2inbufxe
« Previous Showing results 1 — 15 out of 88 results