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In-Memory Computing with Resistive Memory Circuits: Status and Outlook

Giacomo Pedretti, Daniele Ielmini
2021 Electronics  
Finally, we discuss RRAM performance for various analog computing tasks compared to other computational memory devices.  ...  Among the memory devices that have been considered for IMC, the resistive switching memory (RRAM), also known as memristor, is one of the most promising technologies due to its relatively easy integration  ...  Finally, the higher cell resistance could increase the RC delay time for charging the BL.  ... 
doi:10.3390/electronics10091063 doaj:ba04aa5371fc4464a6019d7b358036cd fatcat:p53kxso7sff45a663lugdl723a

Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems

Emilio Pérez-Bosch Quesada, Rocío Romero-Zaliz, Eduardo Pérez, Mamathamba Kalishettyhalli Mahadevaiah, John Reuben, Markus Andreas Schubert, Francisco Jiménez-Molinos, Juan Bautista Roldán, Christian Wenger
2021 Electronics  
Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability.  ...  In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices  ...  RRAM cells.  ... 
doi:10.3390/electronics10060645 fatcat:oqbpowj5zzcxjbf2n25anhceey

A parameterized SPICE macromodel of resistive random access memory and circuit demonstration

Huan-Lin Chang, Hsuan-Chih Li, C. W. Liu, F. Chen, M.-J. Tsai
2011 2011 International Conference on Simulation of Semiconductor Processes and Devices  
(4) unipolar/bipolar mode selection, and (5) multilevel cell (MLC) operation.  ...  A parameterized SPICE macromodel of resistive random acess memory (RRAM) is demonstrated to simulate the memory chip.  ...  The READ driver then sends analog signals BL_OUT to the sense amplifier (SA) for digital signals SA_OUT. Fig. 13 shows the test results of the READ process.  ... 
doi:10.1109/sispad.2011.6034967 fatcat:tzk6rvmcxragrmhw75x3sq27a4

Demonstration and modeling of multi-bit resistance random access memory

Xiang Yang, Albert B. K. Chen, Byung Joon Choi, I-Wei Chen
2013 Applied Physics Letters  
Using a nanometallic bipolar RRAM, we have illustrated a general scheme for writing/rewriting multi-bit memory using voltage pulses.  ...  A multi-bit memory is shown to realize considerable space saving at a modest decrease of switching speed. Disciplines  ...  Thus, the delay time (5Â longer) is still extremely short for a 100 Â 100 nm 2 cell.  ... 
doi:10.1063/1.4790158 fatcat:dza2c47tx5fufn27mjf7kg5s6e

Advances in Emerging Memory Technologies: From Data Storage to Artificial Intelligence

Gabriel Molas, Etienne Nowak
2021 Applied Sciences  
Finally, we discuss how the rise of artificial intelligence and bio-inspired circuits offers an opportunity for emerging memory technology and shifts the application from pure data storage to storage and  ...  The potential of these technologies for storage applications addressing various markets and products is discussed.  ...  Multilevel is difficult to achieve and MRAM requires a good sense amplifier.  ... 
doi:10.3390/app112311254 fatcat:pg4iqzg4yfc2vb2lh2mgkyqafq

NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark

Anni Lu, Xiaochen Peng, Wantong Li, Hongwu Jiang, Shimeng Yu
2021 Frontiers in Artificial Intelligence  
Some adjustment factors are introduced to account for transistor sizing and wiring area in the layout, gate switching activity, post-layout performance drop, etc.  ...  In this study, we validate and calibrate the prediction of NeuroSim against a 40-nm RRAM-based CIM macro post-layout simulations.  ...  ACKNOWLEDGMENTS The authors thank TSMC for providing the 40-nm RRAM tape-out shuttle. Frontiers in Artificial Intelligence | www.frontiersin.org June 2021 | Volume 4 | Article 659060  ... 
doi:10.3389/frai.2021.659060 pmid:34179768 pmcid:PMC8219932 fatcat:fqhvzbq6qfatbeekksfaxgel6u

Resistive Random Access Memory (RRAM): an Overview of Materials, Switching Mechanism, Performance, Multilevel Cell (mlc) Storage, Modeling, and Applications

Furqan Zahoor, Tun Zainal Azni Zulkifli, Farooq Ahmad Khanday
2020 Nanoscale Research Letters  
A discussion on multilevel cell (MLC) storage capability of RRAM, which is attractive for achieving increased storage density and low cost is presented.  ...  In addition, an elaborate description of switching methodologies and current voltage relationships for various popular RRAM models is covered in this work.  ...  Acknowledgments First of all, the authors would like to thank and gratefully acknowledge all corresponding publishers for the kind permission to reproduce their figures and related description used in  ... 
doi:10.1186/s11671-020-03299-9 pmid:32323059 fatcat:p3bp3ahunbe7lont6by333oimi

Low‐Power Computing with Neuromorphic Engineering

Dingbang Liu, Hao Yu, Yang Chai
2020 Advanced Intelligent Systems  
Simulation of PCM to neural cell, and spiking time-dependent plasticity of the biological synapse and PCM. Reproduced with permission.  ...  Multiply accumulation procedure in RRAM crossbar with a sensing amplifier above each column subarray for activation. Reproduced with permission.  ... 
doi:10.1002/aisy.202000150 fatcat:wxbtla4zd5a6ho42xmpix4gv7m

In-memory computing with resistive switching devices

Daniele Ielmini, H.-S. Philip Wong
2018 Nature Electronics  
It has been evaluated that, for many computing tasks, most of the energy and time are consumed in data movement, rather than computation [4] .  ...  analogue and digital circuits.  ...  Correspondence and requests for materials should be addressed to D.I. or H.S.P.W.  ... 
doi:10.1038/s41928-018-0092-2 fatcat:wspycou2s5gexfh6kgzsam52be

Benchmark of Ferroelectric Transistor Based Hybrid Precision Synapse for Neural Network Accelerator

Yandong Luo, Panni Wang, Xiaochen Peng, Xiaoyu Sun, Shimeng Yu
2019 IEEE Journal on Exploratory Solid-State Computational Devices and Circuits  
The benchmark is conducted by multilayer-perceptron (MLP) + NeuroSim framework with comparison to other capacitor-assisted (e.g., 3T1C + 2PCM) hybrid precision cell.  ...  Recently, we proposed a synaptic cell of a ferroelectric transistor (FeFET) with two CMOS transistors (2T1F) that exploit the hybrid precision for training and inference, which overcomes the challenges  ...  ACKNOWLEDGMENT The authors would like to thank Prof. S. Datta's group at the University of Notre Dame for useful discussions and suggestions.  ... 
doi:10.1109/jxcdc.2019.2925061 fatcat:2jorqjvllrb45devat56ftznry

Field-Programmable Crossbar Array (FPCA) for Reconfigurable Computing [article]

Mohammed A. Zidan, YeonJoo Jeong, Jong Hong Shin, Chao Du, Zhengya Zhang, Wei D. Lu
2017 arXiv   pre-print
For decades, advances in electronics were directly driven by the scaling of CMOS transistors according to Moore's law.  ...  The system can be tailored to achieve maximal energy efficiency based on the data flow by dynamically allocating the basic computing fabric for storage, arithmetic, and analog computing including neuromorphic  ...  Dreslinski Jr. for valuable suggestions and fruitful discussions.  ... 
arXiv:1612.02913v4 fatcat:pg4gcagvkjek5callja5dy4xoq

2D Materials Based Optoelectronic Memory: Convergence of Electronic Memory and Optical Sensor

Feichi Zhou, Jiewei Chen, Xiaoming Tao, Xinran Wang, Yang Chai
2019 Research  
Considering the large occupation proportion of image data in both data center and edge devices, a device integration with optical sensing and data storage and processing is highly demanded for future energy-efficient  ...  In addition, its ultrathin body thickness and transfer process at low temperature allow 2D materials to be heterogeneously integrated with other existing materials system.  ...  Although the ORAM exhibits good photo-response, its short retention time (less than 50 s) and low ON/OFF ratio (less than 10) limit the applications for multilevel nonvolatile memories.  ... 
doi:10.34133/2019/9490413 pmid:31549096 pmcid:PMC6750115 fatcat:pzp6gnqkxrhmrm5h5cdjh5xe2a

An 8-bit Radix-4 Non-Volatile Parallel Multiplier

Chengjie Fu, Xiaolei Zhu, Kejie Huang, Zheng Gu
2021 Electronics  
While the presence of RRAM save computational time and overall power as multiplicand is stored beforehand. The area of the proposed non-volatile multiplier is reduced with improved computing speed.  ...  The emerging Resistive Random Access Memory (RRAM) technology has drawn tremendous attention due to its non-volatile ability and the potential in computation application.  ...  For each cell shown in Figure 2 , we use 4 RRAMs with 1T1R configuration to select different booth coding types: ±2A, ±1A or ±0A.  ... 
doi:10.3390/electronics10192358 fatcat:hanymfdfhvd3xalxkkigie7j2e

Emulating the Electrical Activity of the Neuron Using a Silicon Oxide RRAM Cell

Adnan Mehonic, Anthony J. Kenyon
2016 Frontiers in Neuroscience  
Here we demonstrate the feasibility of using the RRAM cell to go further and to model aspects of the electrical activity of the neuron.  ...  Further, we demonstrate that RRAM devices are capable of integrating input current pulses over time to produce thresholded voltage transients.  ...  (B) Time sequence of input to device: Train of excitatory current pulses (4 mA) separated by sensing current pulses (1 uA).  ... 
doi:10.3389/fnins.2016.00057 pmid:26941598 pmcid:PMC4763078 fatcat:74c47wumzjgnlhkkcwwvfjecii

MNSIM: Simulation Platform for Memristor-based Neuromorphic Computing System

Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang
2017 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
MNSIM proposes a general hierarchical structure for memristor-based neuromophic computing system, and provides flexible interface for users to customize the design.  ...  MNSIM also provides a detailed reference design for large-scale applications. MNSIM embeds estimation models of area, power, and latency to simulate the performance of system.  ...  The read circuit can be ADCs or multilevel Sensing Amplifiers (SAs). If the weights of network are bipolar, extra subtractors are needed to merge the signals comes from two crossbars.  ... 
doi:10.1109/tcad.2017.2729466 fatcat:qvlhimwj6fbmpovgtmxa22coy4
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