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Tiered-latency DRAM: A low latency and low cost DRAM architecture

Donghyuk Lee, Yoongu Kim, V. Seshadri, Jamie Liu, L. Subramanian, O. Mutlu
2013 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)  
In this work, we introduce Tiered-Latency DRAM (TL-DRAM), which achieves both low latency and low cost-per-bit.  ...  Specialized low-latency DRAMs use shorter bitlines with fewer cells, but have a higher cost-per-bit due to greater senseampli er area overhead.  ...  Donghyuk Lee is supported in part by a Ph.D. scholarship from Samsung.  ... 
doi:10.1109/hpca.2013.6522354 dblp:conf/hpca/LeeKSLSM13 fatcat:brdw2oc7praanjyh5yiejevyzu

Tiered-Latency DRAM (TL-DRAM) [article]

Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu
2016 arXiv   pre-print
The key goal of TL-DRAM is to provide low DRAM latency at low cost, a critical problem in modern memory systems.  ...  This paper summarizes the idea of Tiered-Latency DRAM, which was published in HPCA 2013.  ...  A Cost-Efficient Low-Latency DRAM.  ... 
arXiv:1601.06903v1 fatcat:jirxfkfcqzhq7ehxtkdmcdpbti

Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture

Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu
2018
In this work, we introduce Tiered-Latency DRAM (TL-DRAM), which achieves both low latency and low cost-per-bit.  ...  Specialized low-latency DRAMs use shorter bitlines with fewer cells, but have a higher cost-per-bit due to greater sense-amplifier area overhead.  ...  Donghyuk Lee is supported in part by a Ph.D. scholarship from Samsung.  ... 
doi:10.1184/r1/6469469.v1 fatcat:x4le2a46q5fatamkotgg7azrmm

Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost [article]

Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu
2018 arXiv   pre-print
To achieve both low latency and low cost per bit, we introduce Tiered-Latency DRAM (TL-DRAM).  ...  Tiered-Latency DRAM has inspired several other works on reducing DRAM latency with little to no architectural modification.  ...  This research was also partially supported by grants from the NSF (grants 0953246 and 1212962), GSRC, and the Intel URO Memory Hierarchy Program.  ... 
arXiv:1805.03048v1 fatcat:e6se3wyaunhtng3x47w7qg6fqe

Rethinking Design Metrics for Datacenter DRAM

Manu Awasthi
2015 Proceedings of the 2015 International Symposium on Memory Systems - MEMSYS '15  
However datacenter scale applications running on server platforms care largely about having access to a large pool of low-latency main memory (DRAM), and in the best case, are unable to utilize even a  ...  Over the years, the evolution of DRAM has provided a little improvement in access latencies, but has been optimized to deliver greater peak bandwidths from the devices.  ...  DISUSSION AND CONCLUSIONS Over the years, commodity DRAM (DDR2, DDR3, DDR4 etc.) has been optimized for (i) low latency, (ii) high bandwidth, and (iii) low cost/bit.  ... 
doi:10.1145/2818950.2818973 dblp:conf/memsys/Awasthi15 fatcat:ttzyoavfe5b3bpn2ii3okjj3w4

Recent Advances in DRAM and Flash Memory Architectures [article]

Onur Mutlu, Saugata Ghose, Rachata Ausavarungnirun
2018 arXiv   pre-print
DRAM and NAND flash memory, the dominant memory and storage technologies, respectively; and (2) several new mechanisms we have proposed based on our observations from these analyses, characterization,  ...  In order to understand the sources of various bottlenecks of the dominant memory and storage technologies, these works perform rigorous studies of device-level and application-level behavior, using a combination  ...  This work (1) proposes a new DRAM architecture that can provide us with the performance benefits of costly reduced-latency DRAM products in a cost-effective manner, by isolating a small portion of a DRAM  ... 
arXiv:1805.09127v3 fatcat:fnutr3affreajggqo6dcwk6b24

In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs

Ho Shin, Eui-Young Chung
2019 Micromachines  
In this paper, we propose two new management algorithms for the in-DRAM caches to achieve a low-latency and low-power 3D-stacked DRAM device.  ...  Although there are various cache management techniques and latency hiding schemes to reduce DRAM access time, in a high-performance system using high-capacity 3D-stacked DRAM, it is ultimately essential  ...  be expanded at a low cost.  ... 
doi:10.3390/mi10020124 pmid:30769837 pmcid:PMC6412702 fatcat:3w5j76nfp5eo7a6e3ztbouuntm

Reducing DRAM Latency at Low Cost by Exploiting Heterogeneity [article]

Donghyuk Lee
2016 arXiv   pre-print
Third, we propose a new technique, Architectural-Variation-Aware DRAM (AVA-DRAM), which reduces DRAM latency at low cost, by profiling and identifying only the inherently slower regions in DRAM to dynamically  ...  First, based on the observation that long bitlines in DRAM are one of the dominant sources of DRAM latency, we propose a new DRAM architecture, Tiered-Latency DRAM (TL-DRAM), which divides the long bitline  ...  In this chapter, we introduce Tiered-Latency DRAM (TL-DRAM), a DRAM architecture that provides both low latency and low cost-per-bit.  ... 
arXiv:1604.08041v1 fatcat:zw4nctympra4fp4cwzkiwbb2ca

Reducing DRAM Access Latency by Exploiting DRAM Leakage Characteristics and Common Access Patterns [article]

Hasan Hassan
2016 arXiv   pre-print
In this thesis, we develop a low-cost mechanism, called ChargeCache, which enables faster access to recently-accessed rows in DRAM, with no modifications to DRAM chips.  ...  DRAM-based memory is a critical factor that creates a bottleneck on the system performance since the processor speed largely outperforms the DRAM latency.  ...  Enhancing DRAM Architecture. Lee at al. propose Tiered-Latency DRAM (TL-DRAM) [48] which divides each subarray into near and far segments using isolation transistors.  ... 
arXiv:1609.07234v1 fatcat:5iuox7vjmndu3dciwbvlzpc5hu

Mitigating the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration [article]

Chao-Hsuan Huang, Ishan G Thakkar
2020 arXiv   pre-print
Over the years, the DRAM latency has not scaled proportionally with its density due to the cost-centric mindset of the DRAM industry.  ...  Based on our evaluation results for PARSEC benchmarks, our designed M3D DRAM cell-array organizations can yield up to 9.56% less latency, up to 4.96% less power consumption, and up to 21.21% less energy-delay  ...  We evaluated the latency-area tradeoffs for various configurations of 2D DDR4 and M3D DRAMs.  ... 
arXiv:2008.11367v1 fatcat:ivyn3eiikbhwdj7vw3npm2sg7q

Reducing DRAM footprint with NVM in facebook

Assaf Eisenman, Darryl Gardner, Islam AbdelRahman, Jens Axboe, Siying Dong, Kim Hazelwood, Chris Petersen, Asaf Cidon, Sachin Katti
2018 Proceedings of the Thirteenth EuroSys Conference on - EuroSys '18  
In this work, we design a key-value store, MyNVM, which leverages an NVM block device to reduce DRAM usage, and to reduce the total cost of ownership, while providing comparable latency and queries-per-second  ...  Our implementation reduces the size of the DRAM cache from 96 GB to 16 GB, and incurs a negligible impact on latency and queries-per-second compared to MyRocks.  ...  ACKNOWLEDGMENTS We thank Kumar Sundararajan, Yashar Bayani, David Brooks, Andrew Kryczka, Banit Agrawal, and Abhishek Dhanotia for their valuable assistance and suggestions.  ... 
doi:10.1145/3190508.3190524 dblp:conf/eurosys/EisenmanGAADHPC18 fatcat:gcatxx6thfdm5bcw5zvwle4lxu

A Survey Of Techniques for Architecting DRAM Caches

Sparsh Mittal, Jeffrey S. Vetter
2016 IEEE Transactions on Parallel and Distributed Systems  
Recent trends of increasing core-count and memory/bandwidth-wall have led to major overhauls in chip architecture.  ...  In this paper, we present a survey of techniques for architecting DRAM caches. Also, by classifying these techniques across several dimensions, we underscore their similarities and differences.  ...  Thus, their study shows that a server-on-chip system is feasible even with a low-cost cooling option which provides opportunity for cost and energy savings in datacenters. Yun et al.  ... 
doi:10.1109/tpds.2015.2461155 fatcat:tqg5hgv64bfnbf6m5c6v4mh5sa

Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency [article]

Hasan Hassan, Gennady Pekhimenko, Nandita Vijaykumar, Vivek Seshadri, Donghyuk Lee, Oguz Ergin, Onur Mutlu
2018 arXiv   pre-print
In this work, we develop a low-cost mechanism, called ChargeCache, that enables faster access to recently-accessed rows in DRAM, with no modifications to DRAM chips.  ...  DRAM latency continues to be a critical bottleneck for system performance.  ...  This work is supported in part by NSF grants 1212962, 1320531, and 1409723, the Intel Science and Technology Center for Cloud Computing, and the Semiconductor Research Corporation.  ... 
arXiv:1805.03969v1 fatcat:dtbttcvk35b67batezwu5f4jxm

Asymmetric DRAM synthesis for heterogeneous chip multiprocessors in 3D-stacked architecture

Minje Jun, Myoung-Jin Kim, Eui-Young Chung
2012 Proceedings of the International Conference on Computer-Aided Design - ICCAD '12  
To tackle this problem, we propose an asymmetric 3D-stacked DRAM architecture where the DRAM die is divided into multiple segments and the segments are optimized for different memory requirements.  ...  Also, since the optimal architecture of the DRAM can be different for different heterogeneous CMPs, we propose an automatic synthesis method for the asymmetric 3D-stacked DRAM architecture.  ...  As tackled in [17] , there necessarily exist a bunch of through-DRAM TSVs in DRAM-stacked processors since the DRAM tiers are located between the processor tier and the package substrate.  ... 
doi:10.1145/2429384.2429399 dblp:conf/iccad/JunKC12 fatcat:vcntfwbcnrbpjh5snodcarruba

Power-Efficient DRAM Speculation

Nidhi Aggarwal, Jason F. Cantin, Mikko H. Lipasti, James E. Smith
2008 High-Performance Computer Architecture  
PEDS takes advantage of information provided by a Region Coherence Array to identify requests that have a high likelihood of obtaining data from another processor's cache, and does not access DRAM speculatively  ...  Although speculatively accessing DRAM has the potential performance advantage of overlapping DRAM latency with the snoop, it wastes power for memory requests that obtain data from other processors' caches  ...  Acknowledgements We thank our many anonymous reviewers for their comments and suggestions. We also thank Prasun Agarwal, Candy Cantin, and Pattabi Seshadri for comments and help proofreading.  ... 
doi:10.1109/hpca.2008.4658649 dblp:conf/hpca/AggarwalCLS08 fatcat:4npkvocmfnajlnu6klbuiqtkm4
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