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Best of both worlds

Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel
2018 Proceedings of the International Conference on Computer-Aided Design - ICCAD '18  
foundries and reverse-engineering by end-users).  ...  We propose a security-driven CAD and manufacturing flow for face-to-face (F2F) 3D ICs, along with obfuscation of interconnects.  ...  Anja Henning-Knechtel for preparing selected illustrations.  ... 
doi:10.1145/3240765.3240784 dblp:conf/iccad/PatnaikASK18 fatcat:pjtt4ja6rnbrnnvfbg2fhm2cdu

A Survey on Chip to System Reverse Engineering

Shahed E. Quadir, Junlin Chen, Domenic Forte, Navid Asadizanjani, Sina Shahbazmohamadi, Lei Wang, John Chandy, Mark Tehranipoor
2016 ACM Journal on Emerging Technologies in Computing Systems  
In this paper, we will be presenting a survey of reverse engineering and anti-reverse engineering techniques on the chip, board, and system levels.  ...  To inhibit reverse engineering (RE) for those with dishonest intentions (e.g., piracy and counterfeiting), it is important that the community is aware of the state-of-the-art capabilities available to  ...  Generally, ROM only provides limited protection against reverse engineering (RE).  ... 
doi:10.1145/2755563 fatcat:uzdampyd6fc2fg2axhn7ydnioi

Hardware Functional Obfuscation With Ferroelectric Active Interconnects [article]

Tonggunag Yu, Yixin Xu, Shan Deng, Zijian Zhao, Nicolas Jao, You Sung Kim, Stefan Duenkel, Sven Beyer, Kai Ni, Sumitha George, Vijaykrishnan Narayanan
2021 arXiv   pre-print
Camouflaging gate techniques are typically used in hardware security to prevent reverse engineering.  ...  Layout level camouflaging by adding dummy contacts ensures some level of protection against extracting the correct netlist.  ...  Erbagci et al. 3 proposed a gate camouflaging technique using threshold voltage defined (TVD) logic topology.  ... 
arXiv:2110.03855v1 fatcat:mropsrqnfzekhcfbc6qjacu4fm

Methodologies to exploit ATPG tools for de-camouflaging

Deepakreddy Vontela, Swaroop Ghosh
2017 2017 18th International Symposium on Quality Electronic Design (ISQED)  
Camouflaging Using Threshold Defined Multiplexer In this section we present the threshold defined multiplexer and key design requirements and obfuscation methodology.  ...  This thesis provides an in-depth analysis of reverse engineering using ATPG tools and also designed of a multiplexer which is used to camouflage the interconnects.  ... 
doi:10.1109/isqed.2017.7918324 dblp:conf/isqed/VontelaG17 fatcat:6nxnu5korngataww5f2jyydv3e

Addressing protection challenges associated with Type 3 and Type 4 wind turbine generators

Bing Chen, Arun Shrestha, Fred A. Ituzaro, Normann Fischer
2015 2015 68th Annual Conference for Protective Relay Engineers  
This paper presents the fault current characteristics of a Type 4 WTG using a detailed MATLAB ® and Simulink ® model that incorporates pseudo control logic for this converter type.  ...  At present, short-circuit analysis tools commonly used by protection engineers are inadequate in representing the fault current behavior of these WTGs.  ...  A forward fault direction is declared if Z2 is less than the forward directional threshold, and a reverse directional fault is declared if Z2 is greater than the reverse directional threshold.  ... 
doi:10.1109/cpre.2015.7102177 fatcat:txrnug3gfvabxe4elzko2ocueq

Use of Directional Elements at the Utility-Industrial Interface

David Costello, Martin Moon, Greg Bow
2006 2006 Power Systems Conference: Advanced Metering, Protection, Control, Communication, and Distributed Resources  
ACKNOWLEDGEMENTS The authors express their sincere appreciation for the experience and expertise shared by F. E.  ...  ., Senior Consultant for Dashiell Corporation, during the research phase of writing this technical paper.  ...  He worked as a system protection engineer for Central and Southwest, and served on the System Protection Task Force for the ERCOT.  ... 
doi:10.1109/psamp.2006.285400 fatcat:vgr7ltnhvze65nw25vurhuxfb4

Coordinating dissimilar line relays in a communications-assisted scheme

William Tucker, Andrew Burich, Michael Thompson, RadhaKiranMaye Anne, Sneha Vasudevan
2014 2014 67th Annual Conference for Protective Relay Engineers  
However, when applying modern POTT schemes that include advanced features such as current reversal and echo logic, reverse blocking elements play an important role and need to be properly coordinated.  ...  Control, and Monitoring of Electric Power Systems, has published numerous technical papers, and has a number of patents associated with power system protection and control.  ...  Protection engineers should always strive to achieve reliable operation of the protection scheme, regardless of whether it involves an interconnecting transmission line.  ... 
doi:10.1109/cpre.2014.6798998 fatcat:pivixvvczvgh5jbhbbznsfg65a

Covert Gates: Protecting Integrated Circuits with Undetectable Camouflaging

Bicky Shakya, Haoting Shen, Mark Tehranipoor, Domenic Forte
2019 Transactions on Cryptographic Hardware and Embedded Systems  
Integrated circuit (IC) camouflaging has emerged as a promising solution for protecting semiconductor intellectual property (IP) against reverse engineering.  ...  We perform a comprehensive security analysis of covert gate, and show that it achieves high resiliency against SAT and test-based attacks at very low overheads.  ...  Acknowledgments This work was supported in part by NSF under grant CNS 1651701 and AFOSR under award number FA9550-14-1-0351.  ... 
doi:10.13154/tches.v2019.i3.86-118 dblp:journals/tches/ShakyaSTF19 fatcat:ljo67r4oizdu3p4ed7ershcu2q

Techniques for Design and Implementation of Secure Reconfigurable PUFs

Mehrdad Majzoobi, Farinaz Koushanfar, Miodrag Potkonjak
2009 ACM Transactions on Reconfigurable Technology and Systems  
However, classical delay-based PUF structures have a number of drawbacks including susceptibility to guessing, reverse engineering, and emulation attacks, as well as sensitivity to operational and environmental  ...  We also show how FPGA-based PUFs can be used for privacy protection. Furthermore, reconfigurability enables the introduction of new techniques for PUF testing.  ...  A unique input/output logic network along with an interconnecting approach is introduced to encumber attempts at reverse engineering or modeling the PUF.  ... 
doi:10.1145/1502781.1502786 fatcat:yteu5mg5n5hzzavjk2izlii6uu

Netlist-level IP protection by watermarking for LUT-based FPGAs

Moritz Schmid, Daniel Ziener, Jurgen Teich
2008 2008 International Conference on Field-Programmable Technology  
We restrict the dynamically addressable part of the logic table, thus freeing space for insertion of signature bits into lookup tables (LUTs).  ...  The method was tested on a Xilinx Virtex-II Pro FPGA and showed low overhead in terms of timing and resources at a reasonable number of watermarked cells.  ...  The opposite direction, from lower to higher abstraction levels, as in T Y ←Z (·), can be achieved by reverse engineering.  ... 
doi:10.1109/fpt.2008.4762385 dblp:conf/fpt/SchmidZT08 fatcat:kxy2u3lxurdq7i4jklrilp3pdm

Container-based design of a Virtual Network Security Function

Marco De Benedictis, Antonio Lioy, Paolo Smiraglia
2018 Zenodo  
Moreover, we present a prototype application of this architecture to implement an HTTP reverse proxy with application-layer filtering capabilities, tailored for the NFV Security-as-a-Service scenario.  ...  Finally, we evaluate the proposed solution in a load-balancing scenario, for increased throughput and availability.  ...  We thank Vincenzo Paolo Bacco (vincenzopaolobacco@gmail.com) for his significant contribution to the design and development of the vNSF prototype.  ... 
doi:10.5281/zenodo.3266000 fatcat:hkfgheoitvg7ba7x2tvbmddqxa

TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing

Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann
2020 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
With the introduced wave-pipelining paths, attackers have to capture gate and interconnect delays during reverse engineering, or to test a huge number of combinational paths to identify the wave-pipelining  ...  With recent advances in reverse engineering, attackers can reconstruct a netlist to counterfeit chips by opening the die and scanning all layers of authentic chips.  ...  interconnects are measured while the netlist is reverse engineered.  ... 
doi:10.1109/tcad.2020.2974338 fatcat:g7bscmolejgybc5nvledawtkhu

Secure remote sensing and communication using digital pufs

Teng Xu, James Bradley Wendt, Miodrag Potkonjak
2014 Proceedings of the tenth ACM/IEEE symposium on Architectures for networking and communications systems - ANCS '14  
We demonstrate the use of the digital PUF on two applications that are crucial for sensor networks: trusted remote sensing and logic obfuscation.  ...  In this paper, we present the digital PUF which is stable in the same sense that digital logic is stable, has a very small footprint and very small timing overhead, and can be easily integrated into existing  ...  are are difficult for the attacker to reverse engineer.  ... 
doi:10.1145/2658260.2658279 dblp:conf/ancs/XuWP14 fatcat:qpv5rrh3sndihnv22kebcvlnuy

Hardware Security for and beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges [article]

Johann Knechtel
2020 arXiv   pre-print
However, with the rise of various emerging technologies, whose main purpose is to overcome the fundamental limitations for scaling and power consumption of CMOS technology, unique opportunities arise also  ...  Next, I review selected emerging technologies, namely (i) spintronics, (ii) memristors, (iii) carbon nanotubes and related transistors, (iv) nanowires and related transistors, and (v) 3D and 2.5D integration  ...  to protect against both, the foundries and the end-users.  ... 
arXiv:2001.08780v2 fatcat:gq5pex62ircgdpeo7p37x3dn7u

Multi‐agent based protection scheme using current‐only directional overcurrent relays for looped/meshed distribution systems

Mohammad Ali Ataei, Mohsen Gitizadeh, Matti Lehtonen, Roozbeh Razavi‐Far
2021 IET Generation, Transmission & Distribution  
All agents can make on-board decisions by exchanging binary data, and do not need a control centre, so the safety of the protection system against one-point failures and cyber-attacks is increased.  ...  This paper proposes a novel distributed intelligent based multi-agent protection scheme, which makes use of current-only directional over current relays as agents for detecting and locating faults and  ...  For any PRA, the decision making logic for fault localization on the bus can be defined as in Table 3 .  ... 
doi:10.1049/gtd2.12234 fatcat:xe5uxc2nirh65cdgundpog4hxu
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