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Threshold Circuits for Iterated Matrix Product and Powering

Carlo Mereghetti, Beatrice Palano
2000 RAIRO - Theoretical Informatics and Applications  
Typical probiems in TC° are: the iterated sum of integers (in TC 2 ), integer division (in TC 3 ), iterated product of integers (in TC4), iterated sum and product of rat ionals, matrix multiplication,  ...  Several arithmetic and linear algebra opérations lie in TC°: the iterated sum and product of integers and rationals, integer division, matrix multiplication, etc. (see [7, 8, 16] ).  ... 
doi:10.1051/ita:2000105 fatcat:qf4stv4pnraxhgq7kdbrazfv6q

Parallel power grid analysis using preconditioned GMRES solver on CPU-GPU platforms

Xue-Xin Liu, Hai Wang, Sheldon X.-D. Tan
2013 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)  
Experimental results on the set of published IBM benchmark circuits and mesh-structured power grid networks show that the GPU-GMRES solver can deliver order of magnitudes speedup over the direct LU solver  ...  In this paper, we propose an efficient parallel dynamic linear solver, called GPU-GMRES, for transient analysis of large power grid networks.  ...  On the other hand, iterative solvers, which mainly depend on simple operations such as matrix-vector multiplication and inner product of vectors, are more amicable for parallelization, especially on GPU  ... 
doi:10.1109/iccad.2013.6691171 dblp:conf/iccad/LiuWT13 fatcat:mr6jyhycdzdvbkfivnaunqkfau

On Threshold Circuits and Polynomial Computation

John H. Reif, Stephen R. Tate
1992 SIAM journal on computing (Print)  
This paper investigates the computational power of Threshold Circuits.  ...  A surprising relationship is uncovered between Threshold Circuits and another class of unbounded fanin circuits which are denoted Finite Field Z P (n)  ...  of rational polynomials, 3. banded matrix inverse, and 4. triangular Toeplitz matrix inverse.  ... 
doi:10.1137/0221053 fatcat:4sagnkbzy5fq5csptjebulmvu4

Parallel GMRES solver for fast analysis of large linear dynamic systems on GPU platforms

Kai He, Sheldon X.-D. Tan, Hengyang Zhao, Xue-Xin Liu, Hai Wang, Guoyong Shi
2016 Integration  
The new solver is very robust and can be applied to power grids with different structures as well as for general analysis problems for large linear dynamic systems with asymmetric matrices.  ...  Experimental results on the set of the published IBM benchmark circuits and mesh-structured power grid networks show that the GPU-GMRES solver can deliver order of magnitudes speedup over the direct LU  ...  On the other hand, iterative solvers, which mainly depend on simple operations such as matrix-vector multiplication and inner product of vectors, are more amicable for parallelization, especially on GPU  ... 
doi:10.1016/j.vlsi.2015.07.005 fatcat:uoqn7an6sfc57isxdutsstzjyq

Preconditioned iterative methods for sparse linear algebra problems arising in circuit simulation

W.D. McQuain, C.J. Ribbens, L.T. Watson, R.C. Melville
1994 Computers and Mathematics with Applications  
Timings and convergence statistics are given for each iterative method and preconditioner.  ...  Several iterative methods which are applicable to nonsymmetric and indefinite problems are applied to a suite of test problems derived from simulations of actual bipolar circuits.  ...  requires, at minimum, storage of 5 vectors of length N, and each iteration requires two preconditioning solves, two matrix-vector products, two inner products and three SAXPY operations.  ... 
doi:10.1016/0898-1221(94)90064-7 fatcat:nill4hlkcbecbc6wm76ih5ewcy

Effect of Wavelet Selection on Periodic Steady-State Analysis

Kris Fedick, Carlos Christoffersen
2020 IEEE Access  
Additionally, a new method for automatically selecting the threshold used when removing low amplitude elements in the Jacobian matrix at each iteration is introduced and tested.  ...  INDEX TERMS Adaptive Jacobian thresholding, circuit simulation, Newton-Raphson method, steady-state analysis, wavelets.  ...  , I M is an M × M identity matrix, and ⊗ represents the Kronecker product.  ... 
doi:10.1109/access.2020.2983736 fatcat:rnqbmhoixrcm7ie44b74yl2hsa

Fast OMP algorithm and its FPGA implementation for compressed sensing‐based sparse signal acquisition systems

Shirshendu Roy, Debiprasad P. Acharya, Ajit K. Sahoo
2021 IET Circuits, Devices & Systems  
circuit consumes very low dynamic power.  ...  The design is implemented for K = 256, N = 1024 using XILINX Virtex6 device and supports maximum of K/4 iterations.  ...  The constant I max stands for maximum iteration count and the parameter ϵ is a threshold to determine stopping criteria.  ... 
doi:10.1049/cds2.12047 fatcat:rs3a4nhajvgthlxobjhvdrexuu

MPIE/MoM Acceleration With a General-Purpose Graphics Processing Unit

Danilo De Donno, Alessandra Esposito, Giuseppina Monti, Luciano Tarricone
2012 IEEE transactions on microwave theory and techniques  
The mixed-potential integral-equation formulation, applied to microstrip circuit modeling, is adopted, and both the impedance matrix computation and the linear system solution of the MoM are accelerated  ...  The best suited method is selected automatically during a thresholding phase, which renders the impedance matrix as sparse as possible.  ...  The code has been tested on two microstrip circuits, a T-junction power-divider and a branch-line coupler.  ... 
doi:10.1109/tmtt.2012.2203924 fatcat:gkj2zv4janbbhmcfm4sv5a2mfy

A NISQ Method to Simulate Hermitian Matrix Evolution

Keren Li, Pan Gao
2022 Entropy  
Based on a NISQ module–layered circuit, we propose a heuristic protocol to simulate Hermitian matrix evolution, which is widely applied as the core for many quantum algorithms.  ...  The two embedded methods, with their own advantages, only require shallow circuits and basic quantum gates.  ...  Result For hermitian matrices evolution, Lie-Trotter products and density matrix evolution provide solutions. We briefly review them here.  ... 
doi:10.3390/e24070899 pmid:35885122 pmcid:PMC9316373 fatcat:wxn6iark2rf7le6klbn4vc5wxq

Supplementary document for A Recurrent Ising Machine in a Photonic Integrated Circuit - 4538445.pdf

Mihika Prabhu, Charles Roques-Carmes, Yichen Shen, Nicholas Harris, Li Jing, Jacques Carolan, Ryan Hamerly, Thomas Baehr-Jones, Michael Hochberg, Vladimir Ceperic
2020 Figshare  
Nonlinear threshold Following the matrix multiplication units, a nonlinear threshold function acts on the output fields to generate the spin input for the subsequent iteration.  ...  matrix multiplication unit (DMMU), nonlinear thresholding, and homodyne detection.  ... 
doi:10.6084/m9.figshare.12155646.v1 fatcat:ut7fpm4q5faajdzflpewia4dsa

TwinPCG: Dual Thread Redundancy with forward Recovery for Preconditioned Conjugate Gradient Methods

Kiril Dichev, Dimitrios S. Nikolopoulos
2016 2016 IEEE International Conference on Cluster Computing (CLUSTER)  
Efficient low-overhead redundancy techniques like algorithm-based fault tolerance for sparse matrix-vector products (SpMxV) have recently been proposed.  ...  For iterative solvers, two major reliable strategies of recovery exist: checkpoint-restart for backward recovery, or some type of redundancy technique for forward recovery.  ...  Aliaga of Universitat Jaume I for providing an initial implementation of CG with Intel MKL and CSR format support, and for answering all related questions.  ... 
doi:10.1109/cluster.2016.86 dblp:conf/cluster/DichevN16 fatcat:xrzcckuopbfklffvrjxw3e4qpe

Towards a NISQ Algorithm to Simulate Hermitian Matrix Exponentiation [article]

Keren Li
2021 arXiv   pre-print
Compared with the method such as product formula and density matrix exponentiation, the PQCs provided in our method require only low depth circuit and easily accessible gates, which benefit experimental  ...  Matrix exponentiation, especially hermitian matrix exponentiation, is an essential element for quantum information processing.  ...  THE FRAMEWORK Lie-Trotter product and density matrix exponentiation provide complete solutions for efficiently simulating matrix exponentiation where the matrices are hermitian.  ... 
arXiv:2105.13610v1 fatcat:i54fn64zznecbcnn6crt5yuqbm

Low-voltage CMOS circuits for analog iterative decoders

C. Winstead, N. Nguyen, V.C. Gaudet, C. Schlegel
2006 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
Iterative decoders, including Turbo decoders, provide near-optimal error protection for various communication channels and storage media.  ...  Index Terms-Analog decoding, iterative decoding, low-density parity check (LDPC) decoder, low voltage, low power, Turbo decoder.  ...  Leung for his assistance with power measurements.  ... 
doi:10.1109/tcsi.2005.859773 fatcat:pwe67lb23jhyrovw25a2tqfgba

Determining the Optimal Location and Number of Voltage Dip Monitoring Devices Using the Binary Bat Algorithm

Mario Šipoš, Zvonimir Klaić, Emmanuel Karlo Nyarko, Krešimir Fekete
2021 Energies  
The proposed algorithm uses a monitor reach area matrix created by short-circuit simulations, and the coefficient of the exposed area.  ...  This paper presents an advanced method for determining the optimal location and the optimal number of voltage dip measuring devices.  ...  The product must be greater than 1 or equal to 1 for each fault position.  ... 
doi:10.3390/en14010255 fatcat:od4ojny5ozcgbpnelmmavuk5um

Variable-Rate FEC Decoder VLSI Architecture for 400G Rate-Adaptive Optical Communication

Vikram Jain, Christoffer Fougstedt, Per Larsson-Edefors
2019 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)  
For this range, a decoder implemented in a 28-nm process technology offers throughputs in excess of 400 Gbps, decoding latencies below 53 ns and a power dissipation of less than 0.95 W (or 1.3 pJ/information  ...  We introduce a variablerate FEC decoder architecture that can operate in several different modes, where each mode is linked to code rate and decoding iterations.  ...  ACKNOWLEDGMENT This work was financially supported by the Knut and Alice Wallenberg Foundation and Vinnova.  ... 
doi:10.1109/icecs46596.2019.8964930 dblp:conf/icecsys/JainFL19 fatcat:kjeawuu7grgovnbpfmpnzhar3y
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