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Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic

Alan Daly, William Marnane
2002 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02  
This paper presents a review of some existing architectures for the implementation of Montgomery modular multiplication and exponentiation on FPGA (Field Programmable Gate Array).  ...  Some new architectures are presented, including a pipelined architecture exploiting the maximum carry chain length of the FPGA which is used to implement the modular exponentiation operation required for  ...  There are three possible parallel inputs to the multiplier depending on the stage of the multiplication, and so the multiplexer must be extended to allow for this.  ... 
doi:10.1145/503048.503055 dblp:conf/fpga/DalyM02 fatcat:r647r4flabdvdebbszen55flae

Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic

Alan Daly, William Marnane
2002 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02  
This paper presents a review of some existing architectures for the implementation of Montgomery modular multiplication and exponentiation on FPGA (Field Programmable Gate Array).  ...  Some new architectures are presented, including a pipelined architecture exploiting the maximum carry chain length of the FPGA which is used to implement the modular exponentiation operation required for  ...  There are three possible parallel inputs to the multiplier depending on the stage of the multiplication, and so the multiplexer must be extended to allow for this.  ... 
doi:10.1145/503053.503055 fatcat:v463j5r37je4pkbaefetlxjcli

Design and Implementation of a Sequential Polynomial Basis Multiplier over GF(2m)

2017 KSII Transactions on Internet and Information Systems  
Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software.  ...  The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay  ...  The proposed m-bit sequential multiplier architecture is scalable and modular and hence suitable for VLSI implementations.  ... 
doi:10.3837/tiis.2017.05.021 fatcat:lstwstb4avabxjnw7zfd643fzi

High-Speed RSA Hardware Based on Barret's Modular Reduction Method [chapter]

Johann Großschädl
2000 Lecture Notes in Computer Science  
This paper presents the basic concepts and design considerations of the RSAγ crypto chip, a high-speed hardware accelerator for long integer modular exponentiation.  ...  The major design goal with the RSAγ was the maximization of performance on several levels, including the implemented hardware algorithms, the multiplier architecture, and the VLSI circuit technique.  ...  The FastMM algorithm is very well suited for hardware implementation as it avoids the division in the modular reduction operation and calculates a modular multiplication by three simple n-bit multiplications  ... 
doi:10.1007/3-540-44499-8_14 fatcat:7eyiauemrzhzrfcen66e4ufwbi

Fpga-Oriented Secure Data Path Design: Implementation of a Public Key Coprocessor

Nele Mentens, Kazuo Sakiyama, Lejla Batina, Ingrid Verbauwhede, Bart Preneel
2006 2006 International Conference on Field Programmable Logic and Applications  
This paper introduces a secure FPGA implementation of a coprocessor for public key cryptography. It supports Elliptic Curve Cryptography (ECC) as well as the older RSA standard.  ...  On the other hand, an implementation of these algorithms should also guarantee side-channel security.  ...  This parallel approach leads to the following hardware requirements for the ECC part of our coprocessor: two modular multipliers and two modular adders.  ... 
doi:10.1109/fpl.2006.311205 dblp:conf/fpl/MentensSBVP06 fatcat:fhw4szm75ranpit2mebsiawmmu

State of the Art Parallel Approaches For Rsa Public Key Based Cryptosystem

Sapna Saxena, Bhanu Kapoor
2015 International Journal on Computational Science & Applications  
In this paper we are presenting the survey of various parallel implementations of RSA algorithm involving variety of hardware and software implementations.  ...  RSA is one of the most popular Public Key Cryptography based algorithm mainly used for digital signatures, encryption/decryption etc.  ...  They proposed an FPGA semi-systolic implementation for the modular exponentiation algorithm which can be applied to RSA algorithm.  ... 
doi:10.5121/ijcsa.2015.5108 fatcat:s6epywcysbbbtd7hunrgykeggi

State of the art parallel approaches for RSA public key based cryptosystem [article]

Sapna Saxena, Bhanu Kapoor
2015 arXiv   pre-print
In this paper we are presenting the survey of various parallel implementations of RSA algorithm involving variety of hardware and software implementations.  ...  RSA is one of the most popular Public Key Cryptography based algorithm mainly used for digital signatures, encryption/decryption etc.  ...  They proposed an FPGA semi-systolic implementation for the modular exponentiation algorithm which can be applied to RSA algorithm.  ... 
arXiv:1503.03593v1 fatcat:ynw4a6wynzg4hi65r3jcnrjn2u

Area- Efficient VLSI Implementation of Serial-In Parallel-Out Multiplier Using Polynomial Representation in Finite Field GF(2m) [article]

Saeideh Nabipour, Gholamreza Zare Fatin, Javad Javidan
2020 arXiv   pre-print
In this paper, a new modified serial-in parallel-out multiplication algorithm with interleaved modular reduction is suggested.  ...  Finite field multiplier is regarded as the bottleneck arithmetic unit for such applications and it is the most complicated operation over finite field GF(2m) which requires a huge amount of logic resources  ...  gate for the five binary fields recommended by NIST which can lead to regularity and modularity of VLSI implementation of finite field multipliers.  ... 
arXiv:2007.08284v1 fatcat:l5c72b75nzf6zcsrgj7zkkczma

Modular exponent realization on FPGAs [chapter]

Jüri PÕldre, Kalle TammemÄe, Marek Mandre
1998 Lecture Notes in Computer Science  
The measures for hardware consumption and execution speed based on argument bit width and algorithm rank are created.  ...  The partitioned blocks are used for implementation approximations of two different multiplier architectures. Examples are provided for 3 families of FPGAs: XC4000, XC6200 and FLEX10k  ...  Conclusions In this paper we have analyzed the implementation of modular exponent calculator on FPGAs. The appropriate algorithm for exponentiation and multiplication has been selected.  ... 
doi:10.1007/bfb0055261 fatcat:ncqz4q2d2jcm5dohud2g2dzb4a

Efficient Hardware Implementation of Finite Fields with Applications to Cryptography

Jorge Guajardo, Tim Güneysu, Sandeep S. Kumar, Christof Paar, Jan Pelzl
2006 Acta Applicandae Mathematicae - An International Survey Journal on Applying Mathematics and Mathematical Applications  
We discuss architectures for three types of finite fields and their special versions popularly used in cryptography: binary fields, prime fields and extension fields.  ...  We summarize algorithms and hardware architectures for finite field multiplication, squaring, addition/subtraction, and inversion for each of these fields.  ...  The hardware architectures for addition/subtraction, multiplication, and inverse were presented for the three different finite fields popularly used in cryptography: binary fields, prime fields and extension  ... 
doi:10.1007/s10440-006-9072-z fatcat:3v7fy6stsfgbrcng3i7pujuhaq

FPGA Implementations of SVM Classifiers: A Review

Shereen Afifi, Hamid GholamHosseini, Roopak Sinha
2020 SN Computer Science  
This article presents a comprehensive survey of hardware architectures used for implementing SVM on FPGA over the period 2010-2019.  ...  Several works attempted to optimize performance and cost by implementing SVM in hardware, especially on field-programmable gate array (FPGA) as it is a promising platform for meeting challenging embedded  ...  Systolic Array Architectures The systolic array architecture is a configurable modular platform that combines both parallelism and pipelining techniques for enhancing computing speed.  ... 
doi:10.1007/s42979-020-00128-9 fatcat:ltddm6vuyjetljmqdaqb3im7y4

Hardware Prototyping Of An Efficient Encryption Engine

Muhammad I. Ibrahimy, Mamun B.I. Reaz, Khandaker Asaduzzaman, Sazzad Hussain
2010 Zenodo  
A simple nested loop addition and subtraction have been used in order to implement the RSA operation.  ...  The hardware design is targeted on Altera STRATIX II device and determined that the flexible key RSA encryption engine can be best suited in the device named EP2S30F484C3.  ...  ACKNOWLEDGMENT The authors would like to express sincere gratitude to the Research Centre, International Islamic University Malaysia  ... 
doi:10.5281/zenodo.1081297 fatcat:n7ketsm77rcutoppih66x3l3gy

Fast RNS division algorithms for fixed divisors with application to RSA encryption

Ching Yu Hung, Behrooz Parhami
1994 Information Processing Letters  
Acknowledgement Careful reading of the manuscript by the referees has led to a significant improvement in our presentation. We thank them for their efforts.  ...  For example, the communication and storage requirements of the algorithm, integration of the binaryresidue and residue-binary conversions into the algorithm, and the possibility of systolic implementation  ...  On the basis of hardware and time complexity, our design competes well with sequential implementation of classical methods.  ... 
doi:10.1016/0020-0190(94)00099-9 fatcat:2gmxmxsj5fhmrlg2hbbakvjidi

Embedment of Montgomery Algorithm on Elliptic Curve Cryptography over RSA Public Key Cryptography

Aswathi Thomas, Ebin M. Manuel
2016 Procedia Technology - Elsevier  
This paper presents a modified Elliptic Curve and RSA cryptosystem by incorporating a newly designed Montgomery multiplier algorithm for better efficiency.  ...  The simulation results show significant improvement in terms of speed and power.  ...  Implementation of RSA The significant part of RSA public key Cryptography is the modular exponentiation.  ... 
doi:10.1016/j.protcy.2016.05.179 fatcat:p3coel2mabf3vbjxo53fqxfwvi

A systolic, linear-array multiplier for a class of right-shift algorithms

P. Kornerup
1994 IEEE transactions on computers  
It is also shown how the multiplier, with some simple back-end connections, can compute modular inverses and perform modular division for a power of two as modulus.  ...  Two such multipliers interconnect to form a purely systolic modulo exponentiator, capable of performing RSA encryption at very high clock frequencies, but with a low gate count and small area.  ...  By combining a systolic modular multiplier for yz with one for zz, operating in parallel, we obtain a systolic exponentiator as shown in Figure 7 .  ... 
doi:10.1109/12.295851 fatcat:qufoe7z6nbaddlelmcoehd7a3a
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