Filters








4,845 Hits in 4.0 sec

Thread-safe dynamic binary translation using transactional memory

JaeWoong Chung, Michael Dalton, Hari Kannan, Christos Kozyrakis
2008 High-Performance Computer Architecture  
Dynamic binary translation (DBT) is a runtime instrumentation technique commonly used to support profiling, optimization, secure execution, and bug detection tools for application binaries.  ...  To eliminate races involving metadata, we propose the use of transactional memory (TM).  ...  Prototype System To evaluate the use of transactions in DBT, we used the Pin dynamic binary translator for x86 binaries [19] .  ... 
doi:10.1109/hpca.2008.4658646 dblp:conf/hpca/ChungDKK08 fatcat:tgpdkrlqzfc5vl74d3r5bfghry

JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional Memory

Marek Olszewski, Jeremy Cutler, J. Gregory Steffan
2007 Parallel Architecture and Compilation Techniques (PACT), Proceedings of the International Conference on  
In this paper we present JudoSTM, a novel dynamic binary-rewriting approach to implementing STM that supports C and C++ code.  ...  Transactional memory (TM) has emerged as a promising programming model allowing programmers to focus on parallelism rather than maintaining correctness and avoiding deadlock.  ...  STM via Dynamic Binary-Rewriting In this paper we introduce JudoSTM, a novel STM system that uses dynamic binary-rewriting (DBR) to instrument applications for transactional execution.  ... 
doi:10.1109/pact.2007.4336226 fatcat:6o4dovq2gfathc27fecew7f7cq

Efficient and Retargetable Dynamic Binary Translation on Multicores

Ding-Yong Hong, Jan-Jan Wu, Pen-Chung Yew, Wei-Chung Hsu, Chun-Chen Hsu, Pangfeng Liu, Chien-Min Wang, Yeh-Ching Chung
2014 IEEE Transactions on Parallel and Distributed Systems  
We proposed two techniques to mitigate those problems: 1) using indirect branch translation caching (IBTC) to avoid frequent accesses to locks, and 2) using lightweight memory transactions to emulate atomic  ...  Dynamic binary translation (DBT) is a core technology to many important applications such as system virtualization, dynamic binary instrumentation, and security.  ...  ACKNOWLEDGMENTS This work was supported in part by Taiwan National Science Council (NSC) grant NSC99-2221-E-001-003-MY3, and was also supported in part by the US National Science Foundation (NSF) grant  ... 
doi:10.1109/tpds.2013.56 fatcat:calerdcplffj7i56sne5yvfdum

Janus: Statically-Driven and Profile-Guided Automatic Dynamic Binary Parallelisation

Ruoyu Zhou, Timothy M. Jones
2019 2019 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)  
Janus uses same-ISA dynamic binary modification to optimise application binaries, controlled by static analysis with judicious use of software speculation and runtime checks that ensure the safety of the  ...  It allows us to parallelise even those loops containing dynamically discovered code.  ...  The dynamic binary modifier reads the rewrite rules it contains and transforms the application at runtime as instructed.  ... 
doi:10.1109/cgo.2019.8661196 dblp:conf/cgo/Zhou019 fatcat:u23nm37usncgrhblqtzwjcpkoy

End-to-end sequential consistency

Abhayendra Singh, Satish Narayanasamy, Daniel Marino, Todd Millstein, Madanlal Musuvathi
2012 2012 39th Annual International Symposium on Computer Architecture (ISCA)  
A processor can easily determine a large fraction of these safe accesses with assistance from static compiler analysis and the hardware memory management unit.  ...  Our design employs an additional unordered store buffer for fast-tracking thread-local stores and allowing later memory accesses to proceed without a memory ordering related stall.  ...  To assist in fast translation, the processor uses a Translation Lookaside Buffer (TLB) in each core. Each TLB entry caches a page table entry for a thread executing on its processor core.  ... 
doi:10.1109/isca.2012.6237045 dblp:conf/isca/SinghNMMM12 fatcat:bmo7mpp465eohp2wm6odiyvs4q

End-to-end sequential consistency

Abhayendra Singh, Satish Narayanasamy, Daniel Marino, Todd Millstein, Madanlal Musuvathi
2012 SIGARCH Computer Architecture News  
A processor can easily determine a large fraction of these safe accesses with assistance from static compiler analysis and the hardware memory management unit.  ...  Our design employs an additional unordered store buffer for fast-tracking thread-local stores and allowing later memory accesses to proceed without a memory ordering related stall.  ...  To assist in fast translation, the processor uses a Translation Lookaside Buffer (TLB) in each core. Each TLB entry caches a page table entry for a thread executing on its processor core.  ... 
doi:10.1145/2366231.2337220 fatcat:ff42wovbhzaera2zmvtcwsc4ta

Transactional memory with strong atomicity using off-the-shelf memory protection hardware

Martín Abadi, Tim Harris, Mojtaba Mehrara
2009 SIGPLAN notices  
Our approach is to use off-the-shelf page-level memory protection hardware to detect conflicts between normal memory accesses and transactional ones.  ...  In contrast, our page-level mechanism lets us be less conservative about how non-transactional accesses are treated; we avoid changes to non-transactional code until a possible conflict is detected dynamically  ...  Darko Kirovski, Venkatesh-Prasad Ranganath, Kapil Vaswani, and Ben Zorn for discussions of the ToleRace and Isolator techniques for handling asymmetric data races,Úlfar Erlingsson for his assistance in using  ... 
doi:10.1145/1594835.1504203 fatcat:jju37gesnvgdxgjqsz3nci3p5u

Transactional memory with strong atomicity using off-the-shelf memory protection hardware

Martín Abadi, Tim Harris, Mojtaba Mehrara
2008 Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '09  
Our approach is to use off-the-shelf page-level memory protection hardware to detect conflicts between normal memory accesses and transactional ones.  ...  In contrast, our page-level mechanism lets us be less conservative about how non-transactional accesses are treated; we avoid changes to non-transactional code until a possible conflict is detected dynamically  ...  Darko Kirovski, Venkatesh-Prasad Ranganath, Kapil Vaswani, and Ben Zorn for discussions of the ToleRace and Isolator techniques for handling asymmetric data races,Úlfar Erlingsson for his assistance in using  ... 
doi:10.1145/1504176.1504203 dblp:conf/ppopp/AbadiHM09 fatcat:vo2x36wpivgqhlv3mmwektd5rm

Runtime parallelization of legacy code on a transactional memory system

Matthew DeVuyst, Dean M. Tullsen, Seon Wook Kim
2011 Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers - HiPEAC '11  
It heavily leverages the optimistic concurrency of transactional memory.  ...  This paper proposes a new runtime parallelization technique, based on a dynamic optimization framework, to automatically parallelize single-threaded legacy programs.  ...  ACKNOWLEDGMENTS The authors would like to thank the anonymous reviewers for many useful suggestions. They would also like to thank Leo Porter for his help with the Transactional Memory model.  ... 
doi:10.1145/1944862.1944882 dblp:conf/hipeac/DeVuystTK11 fatcat:jlopsz7sivaa7jf3cqruthp344

Runtime automatic speculative parallelization

Ben Hertzberg, Kunle Olukotun
2011 International Symposium on Code Generation and Optimization (CGO 2011)  
In contrast to other systems for automatic speculative parallelization, RASP uses dynamic binary translation to optimize applications on-the-fly, without any need for recompilation or source code.  ...  We present Runtime Automatic Speculative Parallelization (RASP), a technique for the dynamic extraction of speculative threads from a running application in a user-transparent fashion.  ...  Registers are communicated through memory using explicit loads and stores, inserted where required by the dynamic binary translator.  ... 
doi:10.1109/cgo.2011.5764675 dblp:conf/cgo/HertzbergO11 fatcat:z4qldi2pbnfrfhojrcwoa2xvom

Hardware tansactional memory support for lightweight dynamic language evolution

Nicholas Riley, Craig Zilles
2006 Companion to the 21st ACM SIGPLAN conference on Object-oriented programming systems, languages, and applications - OOPSLA '06  
We propose the use of hardware transactional memory (HTM) to aid runtimes in evolving more capable and robust execution models while maintaining native code compatibility.  ...  Native extension modules' lack of thread safety is a significant barrier to dynamic languages' effective deployment on current and future multicore and multiprocessor systems.  ...  Binary rewriting or wrapper libraries could be used to trap system calls in user space before they enter the kernel.  ... 
doi:10.1145/1176617.1176758 dblp:conf/oopsla/RileyZ06 fatcat:ghn7hmicevdh7plv7yosemiddi

Design and implementation of transactional constructs for C/C++

Yang Ni, Jeffrey Olivier, Serguei Preis, Bratin Saha, Ady Tal, Xinmin Tian, Adam Welc, Ali-Reza Adl-Tabatabai, Moshe Bach, Sion Berkowits, James Cownie, Robert Geva (+2 others)
2008 Proceedings of the 23rd ACM SIGPLAN conference on Object oriented programming systems languages and applications - OOPSLA '08  
This paper presents a software transactional memory system that introduces first-class C++ language constructs for transactional programming.  ...  The runtime switches a transaction's execution mode dynamically to improve performance and to handle calls to precompiled functions and I/O libraries.  ...  This program breaks when translated to use transactions because of this data race. We rewrote barnes to remove this data race and to make it comply with the emerging C++ memory model [8] .  ... 
doi:10.1145/1449764.1449780 dblp:conf/oopsla/NiWABBCGKNOPSTT08 fatcat:cnv2vx5ih5cmtj6s2x4cjzywz4

Design and implementation of transactional constructs for C/C++

Yang Ni, Jeffrey Olivier, Serguei Preis, Bratin Saha, Ady Tal, Xinmin Tian, Adam Welc, Ali-Reza Adl-Tabatabai, Moshe Bach, Sion Berkowits, James Cownie, Robert Geva (+2 others)
2008 SIGPLAN notices  
This paper presents a software transactional memory system that introduces first-class C++ language constructs for transactional programming.  ...  The runtime switches a transaction's execution mode dynamically to improve performance and to handle calls to precompiled functions and I/O libraries.  ...  This program breaks when translated to use transactions because of this data race. We rewrote barnes to remove this data race and to make it comply with the emerging C++ memory model [8] .  ... 
doi:10.1145/1449955.1449780 fatcat:tc3nls2iwzdyzcb6pscz6ktrui

Efficient Runtime Detection and Toleration of Asymmetric Races

Paruj Ratanaworabhan, Martin Burtscher, Darko Kirovski, Benjamin Zorn, Rahul Nagpal, Karthik Pattabiraman
2012 IEEE transactions on computers  
Asymmetric races are race conditions where one thread correctly acquires and releases a lock for a shared variable while another thread improperly accesses the same variable.  ...  [1] use page-level protection to guarantee strong atomicity in software transactional memory.  ...  I use the term safe memory to refer to the region of memory that holds the local copies of the shared memory data. The safe memory is initially empty.  ... 
doi:10.1109/tc.2011.48 fatcat:icjdr6csgffr3ksxmxro2ehxpm

Automated Use-After-Free Detection and Exploit Mitigation: How Far Have We Gone

Binfa Gui, Wei Song, Hailong Xiong, Jeff Huang
2021 IEEE Transactions on Software Engineering  
mapping. 4.1.2 Static Binary Code Analysis Dynamic binary translation.  ...  In contrast to program representations [20], [26], [27], [28], then various the subsequent dynamic binary translation, static binary analyses  ... 
doi:10.1109/tse.2021.3121994 fatcat:35opzmr2gbg67mnftjkdedm7y4
« Previous Showing results 1 — 15 out of 4,845 results