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Thermal-Aware Floorplanning for Partially-Reconfigurable FPGA-Based Systems

Davide Pagano, Mikel Vuka, Marco Rabozzi, Riccardo Cattaneo, Donatella Sciuto, Marco D. Santambrogio
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015   unpublished
In this work we present a novel thermal aware floorplanner based on both Simulated Annealing (SA) and Mixed-Integer Linear Programming (MILP).  ...  The proposed method takes into account an accurate description of heterogeneous resources and partially reconfigurable constraints of recent FPGAs.  ...  ACKNOWLEDGMENTS This work was partially funded by the European Commission in the context of the FP7 FASTER project (#287804).  ... 
doi:10.7873/date.2015.0806 fatcat:7h4twcx4hreozhmxmil4cag2xu

Thermal Aware Module Placement for Heterogeneous 3D-IC Based FPGAs

Alexander Wold, Dirk Koch, Jim Torresen
2013 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum  
The module placer targets systems designed with a component-based flow and systems using partial run-time reconfiguration using relocatable modules (IP-cores).  ...  The improvement is possible with thermal aware module placement.  ...  In this paper, we introduce a 3D-thermal aware module (IPcore) placer targeting component based and partial run-time reconfigurable systems.  ... 
doi:10.1109/ipdpsw.2013.32 dblp:conf/ipps/WoldKT13 fatcat:jzmw4dyugjdzdlslb7nd7xyutq

FPGA Dynamic and Partial Reconfiguration

Kizheppatt Vipin, Suhaib A. Fahmy
2018 ACM Computing Surveys  
Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs).  ...  We then investigate design flows, and identify the key challenges in making reconfigurable FPGA systems easier to design.  ...  Again, this assumption does not hold for modern FPGAs. In [Montone et al. 2010] , the authors present a reconfiguration-aware "floorplacer".  ... 
doi:10.1145/3193827 fatcat:tbks3e734zdkdceihncpdeawia

Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems [article]

Daniel Ziener
2018 arXiv   pre-print
In this treatise, my research on methods to improve efficiency, reliability, and security of reconfigurable hardware systems, i.e., FPGAs, through partial dynamic reconfiguration is outlined.  ...  In the area of reliability, countermeasures against radiation-induced faults and aging effects for long mission times were investigated and applied to SRAM-FPGA-based satellite systems.  ...  The research has been carried out in collaboration with several doctoral researchers, master and bachelor students from my research group Reconfigurable Computing. In  ... 
arXiv:1809.11156v1 fatcat:6ttulp2tancyvds7fk2coxoptq

Smart technologies for effective reconfiguration: The FASTER approach

M. D. Santambrogio, D. Pnevmatikatos, K. Papadimitriou, C. Pilato, G. Gaydadjiev, D. Stroobandt, T. Davidson, T. Becker, T. Todman, W. Luk, A. Bonetto, A. Cazzaniga (+2 others)
2012 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)  
at run time, the capabilities of partial dynamic reconfiguration.  ...  The goal is that for selected application domains, the FASTER toolchain will be able to reduce the design and verification time of complex reconfigurable systems providing additional novel verification  ...  This scheduler is a reconfiguration-aware scheduler for dynamically partially reconfigurable architectures that can also manage static reconfiguration and multi FPGAs.  ... 
doi:10.1109/recosoc.2012.6322881 dblp:conf/recosoc/SantambrogioPPPGSDBTLBCDS12 fatcat:eplvqvzqmfdirggcfr4qb53neq

Thermal characterization of next-generation workloads on heterogeneous MPSoCs

Arman Iranfar, Federico Terraneo, William Andrew Simon, Leon Dragic, Igor Piljic, Marina Zapater, William Fornaciari, Mario Kovac, David Atienza
2017 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)  
Heterogeneous Multi-Processor Systems-on-Chip (MPSoCs), equipped with a mix of general-purpose cores and reconfigurable fabric for custom acceleration of computational blocks, are key in providing the  ...  Moreover, by using our detailed thermal system characterization we are able to explore different application mappings as well as the thermal limits of such heterogeneous platforms.  ...  ACKNOWLEDGMENT This work has been partially supported by the YINS RTD project (No. 20NA21 150939), funded by with Swiss Confederation Financing and scientifically evaluated by SNSF.  ... 
doi:10.1109/samos.2017.8344642 dblp:conf/samos/IranfarTSDPZFKA17 fatcat:6dkhidd3qverpget3m3uo777ya

2021 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 40

2021 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The Author Index contains the primary entry for each item, listed under the first author's name.  ...  for Partially Reconfigurable FPGAs; TCAD Aug. 2021 1613-1625 Wang, J., and Ye, Y., Ant Colony Optimization-Based Thermal-Aware Adap- tive Routing Mechanism for Optical NoCs; TCAD Sept. 2021 1836-1849  ...  ., +, TCAD Feb. 2021 260-273 DUPRFloor: Dynamic Modeling and Floorplanning for Partially Reconfigu-rable FPGAs.  ... 
doi:10.1109/tcad.2021.3136047 fatcat:ppooj4g65nc2zonj7szclerc2y

A Method for Run-Time Prediction of On-Chip Thermal Conditions in Dynamically Reconfigurable SOPCs

Dimple Sharma, Lev Kirischian, John Kalomiros
2021 International Journal of Reconfigurable Computing  
Autonomous mobile systems nowadays deploy FPGA-based System on Programmable Chips (SoPCs) for supporting their dynamic multitask multimodal workloads.  ...  Dynamically reconfiguring appropriate ASP circuit variants of tasks allow systems to maintain their die temperature in the desired range while taking into account variations in power budget and modes of  ...  configuration bitstreams for the target FPGA in the system memory and can be configured/reconfigured on the partially reconfigurable regions (PRRs) of the FPGA as and when required [3] .  ... 
doi:10.1155/2021/8818788 fatcat:ldj3iwtmtbfuvk2gnayiqgxtiy

Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems

Kenneth M. Zick, John P. Hayes
2012 ACM Transactions on Reconfigurable Technology and Systems  
Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems.  ...  Systems with reconfigurability have unique opportunities for adapting to such effects. Required, however, are low-cost, fine-grained methods for sensing physical parameters.  ...  for equipment donations.  ... 
doi:10.1145/2133352.2133353 fatcat:at6rkewhgnex5ki72s7jgu4a5a

2009 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 28

2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
., Globally Reliable Variation-Aware Sizing Ko, H.  ...  ., +, TCAD Feb. 2009 179-192 Partitioning and Scheduling of Task Graphs on Partially Dynamically Reconfigurable FPGAs.  ...  Cheng, L., +, TCAD Nov. 2009 1777-1781 Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs.  ... 
doi:10.1109/tcad.2009.2036802 fatcat:hxyu2mmrnzfnbi6qlt6bklkgku

2020 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 39

2020 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
., +, TCAD Nov. 2020 3650-3661 Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems.  ...  Vista, J., +, TCAD Oct. 2020 2020-2028 Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems.  ...  Entropy-Directed Scheduling for FPGA High-Level Synthesis. Shen, M., +, TCAD Oct. 2020 2588 -2601 FLASH: Fast, Parallel, and Accurate Simulator for HLS.  ... 
doi:10.1109/tcad.2021.3054536 fatcat:wsw3olpxzbeclenhex3f73qlw4

The RECIPE Approach to Challenges in Deeply Heterogeneous High Performance Systems

Giovanni Agosta, William Fornaciari, David Atienza, Ramon Canal, Alessandro Cilardo, José Flich Cardo, Carles Hernandez Luz, Michal Kulczewski, Giuseppe Massari, Rafael Tornero Gavilá, Marina Zapater
2020 Microprocessors and microsystems  
imposed by the applications and ensuring reliability for both time-critical and throughput-oriented computation that run on deeply heterogeneous accelerator-based systems.  ...  RECIPE (REliable power and time-ConstraInts-aware Predictive management of heterogeneous Exascale systems) is a recently started project funded within the H2020 FETHPC programme, which is expressly targeted  ...  European Union's Horizon 2020 research and innovation programme under the FETHPC grant agreement no. 801137 RECIPE: REliable power and time-ConstraIntsaware Predictive management of heterogeneous Exascale systems  ... 
doi:10.1016/j.micpro.2020.103185 fatcat:kevagp2vdvf6hnus4qnxgxbnxq

Three-dimensional Integrated Circuits: Design, EDA, and Architecture

Guangyu Sun
2011 Foundations and Trends® in Electronic Design Automation  
substrate substrate substrate Device layer Device layer Device layer Device layer Metal layers Metal layers Metal layers Metal layers TSV (Through-Silicon-Via) C4 Pad Microbump 1 These two tables are based  ...  Among all these integration approaches, TSV-based 3D integration has the potential to offer the greatest vertical interconnect density, and therefore is the most promising one among all the vertical interconnect  ...  In this section, we will first describe in detail a thermal-aware 3D floorplanning framework [29] , and then give a quick survey on thermal-aware 3D placement and routing.  ... 
doi:10.1561/1000000016 fatcat:usmthkco4rfavmnlvvmmgxolcq

A monitoring infrastructure for FPGA self-awareness and dynamic adaptation

Carlos Gomez Osuna, Miguel Angel Sanchez Marcos, Pablo Ituero, Marisa Lopez-Vallejo, Marisa López-Vallejo
2012 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)  
FPGAs, which are widely used for fast prototyping and implementation of digital circuits, also suffer from these issues.  ...  Proactive approaches start to appear to achieve self-awareness and dynamic adaptation of these devices. To support these techniques we propose the employment of a multi-purpose sensor network.  ...  , thus providing support for partial reconfiguration.  ... 
doi:10.1109/icecs.2012.6463547 dblp:conf/icecsys/OsunaMIL12 fatcat:xxfuov2o2rc3tnbmc4guyf72ra

Total Ionizing Dose Mitigation by Means of Reconfigurable FPGA Computing

Farouk Smith, Sias Mostert
2007 IEEE Transactions on Nuclear Science  
Therefore, the integrated circuits used for spacecraft electronics must be resistant to radiation.  ...  Thus, we define a partial reconfigurable area inside the FPGA and download it into a specified region of the FPGA device.  ...  With this tool it is possible to define a partial reconfigurable area inside the FPGA and download it into a specified region of the FPGA device [EDSO01].  ... 
doi:10.1109/tns.2007.897402 fatcat:are7ncc555dc5kxbnx43cu6fs4
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