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Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology

Aditya Bansal, Mesut Meterelliyoz, Siddharth Singh, Jung Hwan Choi, Jayathi Murthy, Kaushik Roy
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
Temperature maps of benchmark circuits exhibit close correspondence with dynamic power maps because of confined regions of heat generation separated by low thermal conductivity material.  ...  Accurate prediction of temperature in the early phase of design cycle will give valuable estimation of power/performance/reliability of a circuit block and will guide in the design of more robust circuits  ...  Compact thermal models are generated for standard cell layouts.  ... 
doi:10.1145/1118299.1118362 fatcat:nsugkm324vctvj7g67wzhwz5mu

A New Reliability Evaluation Methodology With Application to Lifetime Oriented Circuit Design

Hamed Sajjadi-Kia, Cristinel Ababei
2013 IEEE transactions on device and materials reliability  
We propose a new circuit level vulnerability and reliability evaluation methodology and utilize it to develop a lifetime aware floorplanning strategy.  ...  dielectric breakdown, negative bias temperature instability, electromigration, thermal cycling, and stress migration.  ...  Any findings and conclusions or recommendations expressed herein are those of the authors and do not necessarily reflect the views of the NSF.  ... 
doi:10.1109/tdmr.2012.2228862 fatcat:4gqaws6i6zhjlm7kc7l2hczwyi

PowerSynth progression on layout optimization for reliability and signal integrity

Yarui Peng, Quang Le, Imam Al Razi, Shilpi Mukherjee, Tristan Evans, H. Alan Mantooth
2020 Nonlinear Theory and Its Applications IEICE  
A generic and scalable constraint-aware layout engine is developed to process generic types of devices, traces, and connectors in power modules.  ...  It uses a series of layout generation and optimization algorithms and various electrical and thermal models to automatically synthesize power module layouts and create a Pareto surface of solutions with  ...  The constraint-aware layout engine with the layout generation algorithms can process a variety of DRC-clean layouts through a generic approach.  ... 
doi:10.1587/nolta.11.124 fatcat:sqvepm4ghncyzcodfbukoozggy

System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3-D MP-SOCs

Sumeet S. Kumar, Arnica Aggarwal, Radhika Sanjeev Jagtap, Amir Zjajo, Rene van Leuken
2014 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The resulting power density of these systems necessitates the inclusion of thermal effects in the architecture space exploration stage of the design process.  ...  Her current research interests include VLSI design, power aware and low power, and energy digital system design.  ...  [9] presented a thermal-aware floorplanner for the 3-D stacked processor cores that considers the power dissipation of the interconnect during floorplan exploration.  ... 
doi:10.1109/tvlsi.2013.2273003 fatcat:mlpcivb3pbh67g6ohulcmpv3ze

Layout level timing optimization by leveraging active area dependent mobility of strained-silicon devices

Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
Use of Strained Silicon devices provides performance improvement equivalent to use of next generation devices, without actually requiring scaling.  ...  Recently (in [1] [2]), the dependence of mobility of a SS MOSFET device on its poly-to-poly distance has been reported.  ...  Examples of such challenges include: leakage power, thermal packaging, yield levels, interconnect delays, and printability issues.  ... 
doi:10.1145/1403375.1403582 fatcat:vwi5mi4ccbbvjaji3sqsrwez6m

Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices

Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
2008 2008 Design, Automation and Test in Europe  
Use of Strained Silicon devices provides performance improvement equivalent to use of next generation devices, without actually requiring scaling.  ...  Recently (in [1] [2]), the dependence of mobility of a SS MOSFET device on its poly-to-poly distance has been reported.  ...  Examples of such challenges include: leakage power, thermal packaging, yield levels, interconnect delays, and printability issues.  ... 
doi:10.1109/date.2008.4484780 dblp:conf/date/ChakrabortySP08 fatcat:ldxdermyyzak5oomyhnu6okxqq

Thermally Aware Design

Yong Zhan, Sanjay V. Kumar, Sachin S. Sapatnekar
2007 Foundations and Trends® in Electronic Design Automation  
Nassif, Vidyasagar Nookala, Haifeng Qian, and Tianpei Zhang.  ...  Acknowledgments The authors gratefully acknowledge the role of their past collaborations with (alphabetically) Charlie Chung-Ping Chen, Brent Goplen, David J. Lilja, Sani R.  ...  Microarchitecture-Driven Floorplanning At early stages of design, there is a strong coupling between physical layout and temperature.  ... 
doi:10.1561/1500000007 fatcat:faxvr2rvl5dsbii5afys7vw4fe

2009 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 28

2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
., and Gielen, G. G. E., Globally Reliable Variation-Aware Sizing Ko, H.  ...  ., +, TCAD Nov. 2009 1777-1781 Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs.  ...  ., +, TCAD April 2009 478-489 Performance and Thermal-Aware Steiner Routing for 3-D Stacked ICs. Pathak, M., +, TCAD Sept. 2009 1373-1386 Power Optimization With Power Islands Synthesis.  ... 
doi:10.1109/tcad.2009.2036802 fatcat:hxyu2mmrnzfnbi6qlt6bklkgku

A New Physical Design Flow for a Selective State Retention Based Approach

Joseph Rabinowicz, Shlomo Greenberg
2021 Journal of Low Power Electronics and Applications  
Although the SSRPG approach mitigates the overhead area and power limitations of the conventional SRPG technique, still both SRPG and SSRPG approaches require a similar extra power grid network for the  ...  Moreover, the physical design implementation of SRPG presents additional wiring due to the extra power supply network and power-gating controls for the state retention logic.  ...  , V T is the thermal voltage, V GS is the voltage between gate and source, and V DS is the voltage between drain and source of a MOSFET transistor.  ... 
doi:10.3390/jlpea11030035 fatcat:aqv24sgadjgnbidijuaoa4p6um

Use of sensitivities and generalized substrate models in mixed-signal IC design

Paolo Miliozzi, Iasson Vassiliou, Edoardo Charbon, Enrico Malavasi
1996 Proceedings of the 33rd annual conference on Design automation conference - DAC '96  
A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced noise.  ...  The circuit has been optimized both at the schematic and at the layout level for power and performance, while its sensitivity to layout parasitics and substrate noise has been minimized.  ...  Analog circuits, on the contrary, are generally sensitive both to thermal and electrically induced switching noise.  ... 
doi:10.1145/240518.240560 dblp:conf/dac/MiliozziVCMS96 fatcat:eqspc4pnn5aoppm7gpr7jkg6d4

Design automation methodology and rf/analog modeling for rf CMOS and SiGe BiCMOS technologies

D. L. Harame, K. M. Newton, R. Singh, S. L. Sweeney, S. E. Strang, J. B. Johnson, S. M. Parker, C. E. Dickey, M. Erturk, G. J. Schulberg, D. L. Jordan, D. C. Sheridan (+6 others)
2003 IBM Journal of Research and Development  
Finally, the unit and integration testing of all of these components is performed thoroughly. This paper describes each of these aspects and provides an overview of associated development work.  ...  Signal integrity is seen as a key issue in typical applications, requiring very accurate interconnect transmission-line modeling and RLC extraction of parasitic effects.  ...  We acknowledge the RFIC design centers in Encinitas, California, and Lowell, Massachusetts, for technology direction and early evaluation of the technology and design kits.  ... 
doi:10.1147/rd.472.0139 fatcat:pejbk72rafbfxkagylkctnet24

Impact of Process and Temperature Variations on Network-on-Chip Design Exploration

Bin Li, Li-Shiuan Peh, Priyadarsan Patra
2008 Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)  
With the continuing scaling of CMOS technologies, process variation is becoming a key factor highly impacting system-level power and temperature.  ...  In this paper, we describe the implementation of an architecture-level early-stage design space exploration tool that incorporates the effect of process and temperature variation for Network-on-chips(NoC  ...  support in Orion and valuable suggestions on this work, Li Shang and Yonghong Yang of Queen's University for their assistance with ISAC thermal simulator, Niraj Jha of Princeton University for insightful  ... 
doi:10.1109/nocs.2008.4492731 fatcat:a76flhoklfdxbic6p7waqgsal4

Leakage Models for High-Level Power Estimation

Domenik Helms, Reef Eilers, Malte Metzdorf, Wolfgang Nebel
2018 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The framework consists of the model itself, a floorplan based temperature and voltage drop model, and a variation engine.  ...  the performance which used to be the most important scaling concern since the advent of MOSFETs.  ...  power, floorplanning for interconnect power, and binding and floorplanning for low leakage (low thermal distribution) is found automatically.  ... 
doi:10.1109/tcad.2017.2760519 fatcat:kchk4i7pwrhndhlaqdy4mlui7m

Key Extraction Using Thermal Laser Stimulation

Heiko Lohrke, Shahin Tajik, Thilo Krachenfels, Christian Boit, Jean-Pierre Seifert
2018 Transactions on Cryptographic Hardware and Embedded Systems  
Thermal laser stimulation (TLS) is a failure analysis technique, which can be deployed by an adversary to localize and read out stored secrets in the SRAM of a chip.  ...  To avert this powerful attack, we propose a low-cost and CMOS compatible countermeasure circuit, which is capable of protecting the BBRAM from TLS attempts even when the FPGA is powered off.  ...  Recent generations of field programmable gate arrays (FPGAs) seem to be appropriate candidates for this, as FPGA vendors have been aware of physical attacks and have integrated several countermeasures  ... 
doi:10.13154/tches.v2018.i3.573-595 dblp:journals/tches/LohrkeTKBS18 fatcat:apyh5zojizb4xipefk3me7pecu

Total Ionizing Dose Mitigation by Means of Reconfigurable FPGA Computing

Farouk Smith, Sias Mostert
2007 IEEE Transactions on Nuclear Science  
Synopsis There is increasing use of commercial components in space technology and it is important to recognize that the space radiation environment poses the risk of permanent malfunction due to radiation  ...  The effect of using the MOSFET device in a radiation environment is that the gate oxide becomes ionized by the dose it absorbs due to the radiation induced trapped charges in the gate-oxide.  ...  Fig 4 . 4 11 Floorplan layout with internal FPGA placement of OR-gate logic cell and IO pins Fig. 5 . 5 1 shows a comparison between normal FPGA operation (Case 1) and FPGA power cycling (Case 2).  ... 
doi:10.1109/tns.2007.897402 fatcat:are7ncc555dc5kxbnx43cu6fs4
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