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Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors

Kiran Puttaswamy, Gabriel H. Loh
2007 2007 IEEE 13th International Symposium on High Performance Computer Architecture  
With our Thermal Herding techniques, the temperature increase is only 12 degrees (29% reduction in the 3D worst-case temperature increase).  ...  Without our Thermal Herding techniques, the worstcase 3D temperature increases by 17 degrees.  ...  Acknowledgments Funding and equipment for this project have been provided by Intel Corporation and a grant from the Microelectronics Advanced Research Corporation (MARCO).  ... 
doi:10.1109/hpca.2007.346197 dblp:conf/hpca/PuttaswamyL07 fatcat:rztjintxqfaebbw3q6zy5strku

Recent thermal management techniques for microprocessors

Joonho Kong, Sung Woo Chung, Kevin Skadron
2012 ACM Computing Surveys  
Floorplanning covers a range of thermal-aware floorplanning techniques for 2D and 3D microprocessors.  ...  Microarchitectural techniques include both static and dynamic thermal management techniques that control hardware structures.  ...  We would like to thank Peter Brownlee Bakkum for his extensive feedback. Finally, we would also like to thank the anonymous referees for their helpful feedback.  ... 
doi:10.1145/2187671.2187675 fatcat:bsvvqax2rbftxivi555mzzc7uy

Exploiting narrow-width values for thermal-aware register file designs

Shuai Wang, Jie Hu, S.G. Ziavras, Sung Woo Chung
2009 2009 Design, Automation & Test in Europe Conference & Exhibition  
Localized heating-up creates thermal hotspots across the chip, with the integer register file ranked as the hottest unit in high-performance microprocessors.  ...  In this paper, we perform a detailed study on the thermal behavior of a low-power value-aware register file (VARF) that is subjected to internal fine-grain hotspots.  ...  Their scheme is targeting at the thermal-aware design in the 3D stacked processors.  ... 
doi:10.1109/date.2009.5090887 dblp:conf/date/WangHZC09 fatcat:gscr7dinmvel5bjqiyngyhvhpa

Token3D: Reducing Temperature in 3D Die-Stacked CMPs through Cycle-Level Power Control Mechanisms [chapter]

Juan M. Cebrián, Juan L. Aragón, Stefanos Kaxiras
2011 Lecture Notes in Computer Science  
In this paper we propose the use of microarchitectural power budget techniques to reduce peak temperature.  ...  for 3D designs.  ...  Therefore, in order to accurately control peak temperature, which is of special interest in 3D-stacked processors as this integration technology exasperates thermal problems, a much tighter control is  ... 
doi:10.1007/978-3-642-23400-2_28 fatcat:vdq2gyfmdfbi5niu3blsk6u7du

Thermal-Aware Task Scheduling for 3D Multicore Processors

Xiuyi Zhou, Jun Yang, Yi Xu, Youtao Zhang, Jianhua Zhao
2010 IEEE Transactions on Parallel and Distributed Systems  
A rising horizon in chip fabrication is the 3D integration technology.  ...  Index Terms-3D processors, thermal-aware scheduling. Ç . X. Zhou is with the  ...  ACKNOWLEDGMENTS The authors would like to thank Professor Xuandong Li of Nanjing University for his inputs and the anonymous reviewers for their constructive comments.  ... 
doi:10.1109/tpds.2009.27 fatcat:lteo3wzo4zgy3bysubfzb25bj4

A modular 3d processor for flexible product design and technology migration

Gabriel H. Loh
2008 Proceedings of the 2008 conference on Computing frontiers - CF '08  
This approach forces one of two undesirable situations: (1) all products must be implemented in, and therefore pay the cost of, 3D or (2) a 3D-implemented processor is designed for the high-end/high-performance  ...  We present a modular processor architecture where 3D can be used to enhance performance within a single unified design and also provides for a more gradual migration path toward fully 3D-integrated designs  ...  Acknowledgments This project was funded by NSF grant CCF-0643500; support was also provided by the Focus Center for Circuit & System Solutions (C2S2), one of five research centers funded under the Focus  ... 
doi:10.1145/1366230.1366261 dblp:conf/cf/Loh08 fatcat:tzgrm6bygndzjl2omqracnulea

Quantifying Architectural Impact of Liquid Cooling for 3D Multi-Core Processors

Hyung-Beom Jang, Ik-Roh Yoon, Cheol-Hong Kim, Seung-Won Shin, Sung-Woo Chung
2012 JSTS Journal of Semiconductor Technology and Science  
For future multi-core processors, 3D integration is regarded as one of the most promising techniques since it improves performance and reduces power consumption by decreasing global wire length.  ...  However, 3D integration causes serious thermal problems since the closer proximity of heat generating dies makes existing thermal hotspots more severe.  ...  For these reasons, the 3D integration technique makes existing thermal hotspots worse and creates new thermal hotspots [45] .  ... 
doi:10.5573/jsts.2012.12.3.297 fatcat:hxvqzug26bhexedpk7frxst57i

Temperature-Aware Design and Management for 3D Multi-Core Architectures

Mohamed M. Sabry
2014 Foundations and Trends® in Electronic Design Automation  
Thomas Brunschwiler from IBM Zurich, for their support with the discussions on the liquid cooling modeling and experiments of the different thermal management strategies of 3D MPSoC stacks with liquid  ...  This work was supported in part by the Swiss Confederation under the TRANSCEND Nano-Tera Strategic Action and the CMOSAIC RTD project, as well as the EC in the 7th Framework Program under the GreenDataNet  ...  Another work utilizes various microarchitectural techniques to control the thermal hot spots in 3D MPSoCs via thermal herding [68] .  ... 
doi:10.1561/1000000032 fatcat:niq3pl6tjzfn5aewn3ruskrk5u

TRINITY: Coordinated Performance, Energy and Temperature Management in 3D Processor-Memory Stacks [article]

Karthik Rao and William Song and Yorai Wardi and Sudhakar Yalamanchili
2018 arXiv   pre-print
The consistent demand for better performance has lead to innovations at hardware and microarchitectural levels. 3D stacking of memory and logic dies delivers an order of magnitude improvement in available  ...  Using a cache coherent multicore processor cycle level simulator coupled with power and thermal estimation tools, we investigate the interactions between (a) thermal behaviors (b) compute and memory microarchitecture  ...  ACKNOWLEDGEMENTS This work was supported in part by the National Science Foundation under Grant CNS 0855110 and the Oak Ridge National Laboratory  ... 
arXiv:1808.09087v2 fatcat:364bi4wzxvarzo4igbxp33zjly

Three-dimensional Integrated Circuits: Design, EDA, and Architecture

Guangyu Sun
2011 Foundations and Trends® in Electronic Design Automation  
Metal layers TSV (Through-Silicon-Via) C4 Pad Microbump 1 These two tables are based on IBM 65nm technology for high performance microprocessor design 3 Benefits of 3D Integrated Circuits The following  ...  As the fabrication of 3D integrated circuits has become viable, developing CAD tools and architectural techniques are imperative for the successful adoption of 3D integration technology.  ...  Puttaswamy et al proposed thermal herding techniques for the fine-grain partitioned 3D microarchitecture.  ... 
doi:10.1561/1000000016 fatcat:usmthkco4rfavmnlvvmmgxolcq

Fighting fire with fire

Susmit Biswas, Mohit Tiwari, Timothy Sherwood, Luke Theogarajan, Frederic T. Chong
2011 Proceeding of the 38th annual international symposium on Computer architecture - ISCA '11  
Local thermal hot-spots in microprocessors lead to worstcase provisioning of global cooling resources, especially in large-scale systems.  ...  valid OMB control number.  ...  [25] propose Thermal Herding technique that reduces 3D power density by placing highly switching 16-bits closer to the heat sink, and thereby, reducing the occurrences of hot-spots as well.  ... 
doi:10.1145/2000064.2000104 dblp:conf/isca/BiswasTSTC11 fatcat:u6clkkg2ivgcxpul2vgctm5t6i

Fighting fire with fire

Susmit Biswas, Mohit Tiwari, Timothy Sherwood, Luke Theogarajan, Frederic T. Chong
2011 SIGARCH Computer Architecture News  
Local thermal hot-spots in microprocessors lead to worstcase provisioning of global cooling resources, especially in large-scale systems.  ...  valid OMB control number.  ...  [25] propose Thermal Herding technique that reduces 3D power density by placing highly switching 16-bits closer to the heat sink, and thereby, reducing the occurrences of hot-spots as well.  ... 
doi:10.1145/2024723.2000104 fatcat:hunzp5knebh2rbymrscmkv3dc4