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ThermOS: System support for dynamic thermal management of chip multi-processors

Filippo Sironi, Martina Maggio, Riccardo Cattaneo, Giovanni F. Del Nero, Donatella Sciuto, Marco D. Santambrogio
2013 Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques  
We propose ThermOS, an extension for commodity operating systems that harnesses formal feedback control and idle cycle injection to decrease thermal emergencies while showing better efficiency than commodity  ...  Researchers started investigating dynamic thermal management techniques to address the tradeoff between performance and temperature.  ...  Nacci, and the anonymous referees for their help and invaluable comments. This work was partially supported by the Swedish Research Council through the LCCC Linnaeus Center.  ... 
doi:10.1109/pact.2013.6618802 dblp:conf/IEEEpact/SironiMCNSS13 fatcat:hfdq7qpvwnglpn7oiuhi7vrawq

Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management

Changyun Zhu, Zhenyu Gu, Li Shang, R.P. Dick, R. Joseph
2008 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
power characteristics and processor core thermal characteristics should be exploited; and 2) it proposes an efficient proactive continuously engaged hardware and operating system thermal management technique  ...  However, the stacked highpower density layers of 3-D CMPs increase the importance and difficulty of thermal management.  ...  [23] explored the benefit of OS thermal management for simultaneous multi-threading (SMT) and CMPs.  ... 
doi:10.1109/tcad.2008.925793 fatcat:lzzujkiit5gxhlf5jcstwz5xoi

Power and thermal constraints of modern system-on-a-chip computer

Efraim Rotem, Ran Ginosar, Avi Mendelson, Uri C. Weiser
2013 19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)  
For high end processors, junction temperature has been considered the toughest physical constraint that needs to be tightly managed.  ...  In this paper we describe the major physical constraints, design considerations and modern power and thermal management techniques and demonstrate them on an Intel Core(tm) i7 system.  ...  Acknowledgements This work was supported by "ICRI-CI" -Intel Collaborative Research Institute for Computational Intelligence" 20 40  ... 
doi:10.1109/therminic.2013.6675226 fatcat:rnothx3pmvb5xeelrqyvxtacrq

Power and thermal constraints of modern system-on-a-chip computer

Efraim Rotem, Ran Ginosar, Avi Mendelson, Uri C. Weiser
2015 Microelectronics Journal  
For high end processors, junction temperature has been considered the toughest physical constraint that needs to be tightly managed.  ...  In this paper we describe the major physical constraints, design considerations and modern power and thermal management techniques and demonstrate them on an Intel Core(tm) i7 system.  ...  Acknowledgements This work was supported by "ICRI-CI" -Intel Collaborative Research Institute for Computational Intelligence" 20 40  ... 
doi:10.1016/j.mejo.2015.09.002 fatcat:hivt5kc6trhpjafozhtiw6vape

Nanoelectronics: challenges and opportunities

Giovanni de Micheli
2007 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)  
effects • Keep chip as cool as possible -Reduce failure rates and power consumption • In multi processor (core) system, power management shuts down idle cores -The temperature distribution will  ...  Dynamic voltage scaling in processors • Razor [Austin -U Michigan] -Dynamic latency adjustment for NoCs • Terror [Tamhankar -Stanford] • Autonomic computing -Systems that understand and react  ...  built-in fault tolerance and predictable delays -On chip networks to provide units with structured communication -3-dimensional packages to support integration of different technologies • Novel design  ... 
doi:10.1109/vdat.2007.373195 fatcat:k4vwrb26c5a7rjfscrmm6ykrae

Nanoelectronics: Challenges and Opportunities [chapter]

Giovanni De Micheli
2006 Lecture Notes in Computer Science  
effects • Keep chip as cool as possible -Reduce failure rates and power consumption • In multi processor (core) system, power management shuts down idle cores -The temperature distribution will  ...  Dynamic voltage scaling in processors • Razor [Austin -U Michigan] -Dynamic latency adjustment for NoCs • Terror [Tamhankar -Stanford] • Autonomic computing -Systems that understand and react  ...  built-in fault tolerance and predictable delays -On chip networks to provide units with structured communication -3-dimensional packages to support integration of different technologies • Novel design  ... 
doi:10.1007/11847083_64 fatcat:tj4u5fm3jbazplfvxy5dtatndy

McFTP: A Framework to Explore and Prototype Multi-core Thermal Managements on Real Processors

Long Cheng, Zhihao Zhao, Kai Huang, Gang Chen, Alois Knoll
2017 2017 IEEE Trustcom/BigDataSE/ICESS  
Nowadays, multi-core processor architectures have been widely adopted in main domains e.g., embedded, general-purpose, realtime systems, etc.  ...  With these features, McFTP can not only implement a thermal management policy at high-level of abstraction, but also execute the user-defined task-set for real thermal evolution.  ...  It also supports processors of homogeneous and heterogeneous multi-core architectures.  ... 
doi:10.1109/trustcom/bigdatase/icess.2017.316 dblp:conf/trustcom/ChengZHCK17 fatcat:ycyfnlbpcnbgdkljosvf64xone

Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling

Pablo G. Del Valle, David Atienza
2011 Microelectronics Journal  
New tendencies envisage 2D/3D Multi-Processor System-On-Chip (MPSoC) as a promising solution for the consumer electronics market.  ...  control, under transient and dynamic thermal maps.  ...  Luca Benini at Bologna University, and the group of Advanced Packaging Technologies at IBM Zürich for their useful feedback and inputs in the validation of the 3D thermal modeling and liquid cooling technology  ... 
doi:10.1016/j.mejo.2010.08.003 fatcat:ypcm3n4wcjagxp5xn2z7rkdtfm

Implications of Integrated CPU-GPU Processors on Thermal and Power Management Techniques [article]

Kapil Dev, Indrani Paul, Wei Huang, Yasuko Eckert, Wayne Burleson, and Sherief Reda
2018 arXiv   pre-print
Using detailed thermal and power maps of the die from infrared imaging, we demonstrate that in contrast to traditional multi-core CPUs, heterogeneous processors exhibit higher coupled behavior for dynamic  ...  Heterogeneous processors with architecturally different cores (CPU and GPU) integrated on the same die lead to new challenges and opportunities for thermal and power management techniques because of shared  ...  Modern processors have two main knobs of thermal and power management: dynamic voltage and frequency scaling (DVFS), and scheduling of workloads on different compute units of the chip [11] , [12] .  ... 
arXiv:1808.09651v1 fatcat:jj3gg5ndxbgrxgql36bp4aoofe

Hierarchical Thermal Management Policy for High-Performance 3D Systems With Liquid Cooling

Francesco Zanini, Mohamed M. Sabry, David Atienza, Giovanni De Micheli
2011 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
We consider specifically 3D multi-processor systems-on-chips (MPSoCs), realized by stacking silicon CMOS chips and interconnecting them by means of through-silicon vias (TSVs).  ...  In this paper, we propose a novel online thermal management policy for high-performance 3D systems with liquid cooling.  ...  Brunschwiler for their suggestions.  ... 
doi:10.1109/jetcas.2011.2158272 fatcat:pt4olh4donardmbn3a7aagshpm

Introspective 3D chips

Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Tim Sherwood
2006 Proceedings of the 12th international conference on Architectural support for programming languages and operating systems - ASPLOS-XII  
Many of these tools require full-system data which covers multiple interacting threads, processes, and processors.  ...  In this paper we describe the advantage of using inter-die vias for introspection and we quantify the impact they can have in terms of the area, power, temperature, and routability of the resulting systems  ...  Acknowledgments The authors would like to thank the anonymous reviewers for their helpful feedback.  ... 
doi:10.1145/1168857.1168890 dblp:conf/asplos/MysoreASLBS06 fatcat:k37ttdokjbcv7dwbvsf76qozsu

Introspective 3D chips

Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Tim Sherwood
2006 ACM SIGOPS Operating Systems Review  
Many of these tools require full-system data which covers multiple interacting threads, processes, and processors.  ...  In this paper we describe the advantage of using inter-die vias for introspection and we quantify the impact they can have in terms of the area, power, temperature, and routability of the resulting systems  ...  Acknowledgments The authors would like to thank the anonymous reviewers for their helpful feedback.  ... 
doi:10.1145/1168917.1168890 fatcat:ziwgrfgdtbaabk2mg6nodnbtkq

Introspective 3D chips

Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Tim Sherwood
2006 SIGARCH Computer Architecture News  
Many of these tools require full-system data which covers multiple interacting threads, processes, and processors.  ...  In this paper we describe the advantage of using inter-die vias for introspection and we quantify the impact they can have in terms of the area, power, temperature, and routability of the resulting systems  ...  Acknowledgments The authors would like to thank the anonymous reviewers for their helpful feedback.  ... 
doi:10.1145/1168919.1168890 fatcat:higavctwyvadzilfzu3hly6uxu

Introspective 3D chips

Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Tim Sherwood
2006 SIGPLAN notices  
Many of these tools require full-system data which covers multiple interacting threads, processes, and processors.  ...  In this paper we describe the advantage of using inter-die vias for introspection and we quantify the impact they can have in terms of the area, power, temperature, and routability of the resulting systems  ...  Acknowledgments The authors would like to thank the anonymous reviewers for their helpful feedback.  ... 
doi:10.1145/1168918.1168890 fatcat:i4yhhb5sanhkrismf6vfiw5bc4

The Case for Lifetime Reliability-Aware Microprocessors

Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers
2004 SIGARCH Computer Architecture News  
Using RAMP, we show that this can save cost and/or improve performance, that dynamic voltage scaling is an effective response technique for DRM, and that dynamic thermal management neither subsumes nor  ...  RAMP is based on state-of-the-art device models for different wearout mechanisms.  ...  Acknowledgments We would like to thank Chao-Kun Hu, Barry Linder, and Ernest Wu of IBM for their help with the electromigration and TDDB models.  ... 
doi:10.1145/1028176.1006725 fatcat:dr7zwnxrhvhg3fr5iedyrhpr2e
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