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Theoretical constraints on multidimensional retiming design techniques

Nelson L. Passos, Delvin C. Defoe, Reynold J. Bailey, Ranette Halverson, Richard P. Simpson, Stephen K. Park, Zia-ur Rahman, Robert A. Schowengerdt
2001 Visual Information Processing X  
, multidimensional (MD) retiming.  ...  While many have written about the multi-dimensional retiming technique, no results have been published on the possible limitations of its application.  ...  An effective technique in increasing the computing performance of such applications has been the design and use of ASICs using loop transformation techniques, and in particular, multi-dimensional retiming  ... 
doi:10.1117/12.438262 dblp:conf/spieVIP/PassosDBHS01 fatcat:aehielbrxfcyjbuedx6ehk5pnm

Timing and Code Size Optimization on Achieving Full Parallelism in Uniform Nested Loops [article]

Yaroub Elloumi, Mohamed Akil, Mohamed Hedi Bedoui
2012 arXiv   pre-print
Multidimensional Retiming is one of the most important optimization techniques to improve timing parameters of nested loops.  ...  In this paper, we present a new Multidimensional Retiming technique, called "Optimal Multidimensional Retiming" (OMDR).  ...  THEORY OF OPTIMAL MULTIDIMENSIONAL RETIMING In this section, we present the theoretical foundation of our proposal MDR technique "Optimal Multidimensional Retiming".  ... 
arXiv:1205.4672v1 fatcat:tva6xokazral7cv6dv66uhkwhu

Loop pipelining for scheduling multi-dimensional systems via rotation

Nelson Luiz Passos, Edwin Hsing-Mean Sha, Steven C. Bass
1994 Proceedings of the 31st annual conference on Design automation conference - DAC '94  
technique we developed.  ...  This paper explores the basic properties of MD loop pipelining and presents an algorithm, called multi-dimensional r otation scheduling, to nd an e cient s c hedule based on the multi-dimensional retiming  ...  This paper develops a method for scheduling cyclic MDFGs with resource constraints. We call this technique multidimensional rotation scheduling, generalizing the 1-D rotation method 1 .  ... 
doi:10.1145/196244.196475 dblp:conf/dac/PassosSB94 fatcat:sjio4i2zwjeljgrdms2hi42asu

WCET nested-loop minimization in terms of instruction-level-parallelism

Yaroub Elloumi, Mohamed Akil, Mohamed Hedi Bedoui
2015 2015 International Conference on High Performance Computing & Simulation (HPCS)  
In particular, the Multidimensional Retiming (MR) is an important optimization approach that offers several instruction-level-parallelism solutions.  ...  Secondly, the optimization heuristic implementations show an average improvement on number of cores of 27.18% compared to full parallel ones.  ...  The delayed MR technique [14, 27] proposes a theoretical approach to select and retime paths.  ... 
doi:10.1109/hpcsim.2015.7237066 dblp:conf/ieeehpcs/ElloumiAB15 fatcat:nnnd7akgvjbw3hhvbyy6smxdue

Timing optimization via nest-loop pipelining considering code size

Qingfeng Zhuge, Chun Jason Xue, Meikang Qiu, Jingtong Hu, Edwin H.-M. Sha
2008 Microprocessors and microsystems  
While multidimensional (MD) retiming can explore the outer loop parallelism, it introduces large overheads in loop index generation and code size due to loop transformation.  ...  The average code size is reduced by 69.5% compared with that generated by the MD retiming technique.  ...  If the software-pipelined code cannot be fit into on-chip memory, a designer, without proper techniques, may have to give up using software pipelining, resulting in a design with a deteriorated timing  ... 
doi:10.1016/j.micpro.2008.02.002 fatcat:enzzpxns5rdq7bpr326j6finnq

VHDL design optimization for two-dimensional filters

Nelson L. Passos, Jian Song, Robert P. Light, Ranette Halverson, Richard P. Simpson, Sethuraman Panchanathan, V. Michael Bove, Jr., Subramania I. Sudharsanan
1999 Media Processors 2000  
Based on the retiming information, predicate registers are designed as shift registers that allow the correct execution of the filter function.  ...  Current commercial systems use branch predication techniques, which can also be applied in the design of ASIC systems.  ...  The chained MD retiming technique [13] is one of the possible methods able to compute a legal MD retiming of an MDFG, and to produce a fully parallel graph.  ... 
doi:10.1117/12.375245 fatcat:3qmldbjmtbh7doeilcijq7odnq

A framework for enhancing data reuse via associative reordering

Kevin Stock, Martin Kong, Tobias Grosser, Louis-Noël Pouchet, Fabrice Rastello, J. Ramanujam, P. Sadayappan
2013 Proceedings of the 35th ACM SIGPLAN Conference on Programming Language Design and Implementation - PLDI '14  
We develop a multi-dimensional retiming formalism to characterize the space of valid implementations in conjunction with other program transformations.  ...  The freedom to reorder computations involving associative operators has been widely recognized and exploited in designing parallel algorithms and to a more limited extent in optimizing compilers.  ...  Unleashing the Power of Retiming So far in our framework we have not discussed the legality of retiming, i.e., the constraints on the retiming vectors to ensure the semantics of the program are preserved  ... 
doi:10.1145/2594291.2594342 dblp:conf/pldi/StockKGPRRS14 fatcat:z5kxavwrczdilgay2ojajsqm7m

A framework for enhancing data reuse via associative reordering

Kevin Stock, Martin Kong, Tobias Grosser, Louis-Noël Pouchet, Fabrice Rastello, J. Ramanujam, P. Sadayappan
2014 SIGPLAN notices  
We develop a multi-dimensional retiming formalism to characterize the space of valid implementations in conjunction with other program transformations.  ...  The freedom to reorder computations involving associative operators has been widely recognized and exploited in designing parallel algorithms and to a more limited extent in optimizing compilers.  ...  Unleashing the Power of Retiming So far in our framework we have not discussed the legality of retiming, i.e., the constraints on the retiming vectors to ensure the semantics of the program are preserved  ... 
doi:10.1145/2666356.2594342 fatcat:3eebgmugjndh5aadzriryrgeku

Timing optimization of nested loops considering code size for DSP applications

Qingfeng Zhuge, Zili Shao, E.H.-M. Sha
2004 International Conference on Parallel Processing, 2004. ICPP 2004.  
Software pipelining for nested loops remains a challenging problem for embedded system design.  ...  The experimental results show that our technique outperforms both the standard software pipelining and MD retiming significantly. b(i,j) = a(i,j) + 1.; endfor endfor d(i,j) = c(i,j) + 2.; for i=0 to m  ...  technique, chained MD retiming ("Chained"), and the SPINE-FULL algorithm ("SPINE"), on a simulated system without resource constraint.  ... 
doi:10.1109/icpp.2004.1327957 dblp:conf/icpp/ZhugeSS04 fatcat:ylbqstu22jfsbdz522z2dz5ase

Power and Area Minimization for Multidimensional Signal Processing

Dejan Markovic, Borivoje Nikolic, Robert W. Brodersen
2007 IEEE Journal of Solid-State Circuits  
The design framework is based on a unified, block-based graphical description of the algorithm to avoid design re-entry in various phases of chip development.  ...  The use of architectural techniques for minimization of power and area for complex signal processing algorithms is demonstrated using this framework.  ...  Loop retiming is a technique of distributing pipeline registers around recursive loops [24] .  ... 
doi:10.1109/jssc.2007.892191 fatcat:jf7erdcnu5g65ldis5wkalskwi

Combined partitioning and data padding for scheduling multiple loop nests

Zhong Wang, Edwin H.-M. Sha, Xiaobo (Sharon) Hu
2001 Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '01  
Traditional loop partition techniques, however, consider only a singleton nested loop.  ...  Therefore, our technique can be applied in architectures with low associativity cache.  ...  A multidimensional retiming r is a function that redistributes the nodes in the iteration space. A new LDG is created after the retiming.  ... 
doi:10.1145/502225.502228 fatcat:nge25mjqibecfiganrifyi46hq

Combined partitioning and data padding for scheduling multiple loop nests

Zhong Wang, Edwin H.-M. Sha, Xiaobo (Sharon) Hu
2001 Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '01  
Traditional loop partition techniques, however, consider only a singleton nested loop.  ...  Therefore, our technique can be applied in architectures with low associativity cache.  ...  A multidimensional retiming r is a function that redistributes the nodes in the iteration space. A new LDG is created after the retiming.  ... 
doi:10.1145/502217.502228 dblp:conf/cases/WangSH01 fatcat:33bvcvzgpnbytmwz24p5svcuum

Introduction to the special issue on low power wireless communications

S. Kiaei, E.G. Friedman
1997 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
A multidimensional design space is described in which an appropriate implementation strategy is determined based on specific technological and systems parameters.  ...  Net energy savings of up to 50% with a two times speedup is achievable with this filter design technique.  ...  He has authored two book chapters and many papers in the fields of high speed and low power CMOS design techniques, pipelining and retiming, and the theory and application of synchronous clock distribution  ... 
doi:10.1109/tcsii.1997.868450 fatcat:sfufvk2l3vgodasmp6julwpuyq

On Exploring Inter-Iteration Parallelism Within Rate-Balanced Multirate Multidimensional DSP Algorithms

Mi Lu
2021 figshare.com  
Although the notion of the parallelism in multidimensionalapplications has existed for a long time, it is so farunknown what the bound (if any) of inter-iteration parallelism in multirate multidimensional  ...  This paper explores the bound of inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms and proves that this parallelism can always be achieved in hardware system given  ...  Within such circumstances, this paper makes contributions for a theoretical understanding of the parallelism exploitation which is essential in designs of hardware implementations for multidimensional  ... 
doi:10.6084/m9.figshare.13641440.v1 fatcat:j7sj5o3nkfg6vffsnwrwnpuzny

Logic Synthesis [chapter]

2017 Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology  
ACKNOWLEDGMENT e authors thank Vladimir Yutsis for his helpful feedback on Section 1.5.2.  ...  A global router with a theoretical bound on the optimal solution. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(2):208-216, 2006. 43. D. Müller, K. Radke, and J.  ...  Newton, Retiming for DSM with area-delay trade-offs and delay constraints, Proceedings of ACM/IEEE Design Automation Conference, New Orleans, LA, 1999, pp. 725-730. 205. C. Chu, E. Young, D.  ... 
doi:10.1201/9781315215112-13 fatcat:me52zpnxyfcczh3choo2p4zulm
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