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Single-fault fault-collapsing analysis in sequential logic circuits

J.E. Chen, C.L. Lee, W.Z. Shen
1991 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
relationship which is valid in combinational circuits but no longer valid in sequential circuits.  ...  A fault-collapsing procedure is proposed to collapse faults in sequential circuits.  ...  ACKNOWLEDGMENT The authors wish to express their gratitude for helpful comments from the reviewers.  ... 
doi:10.1109/43.103505 fatcat:qagnul5zmzdvvetbeibdirmrte

Test generation for primitive path delay faults in combinational circuits

Tekumalla, Menon
1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97  
This paper presents a method of identifying primitive path-delay faults in combinational circuits, and deriving robust tests for all robustly testable primitive faults.  ...  Sensitization conditions determined for primitive fault identification are also used in test generation, reducing test generation effort.  ...  the collapsed form expression are sufficient for identifying all primitive faults in the circuit.  ... 
doi:10.1109/iccad.1997.643605 dblp:conf/iccad/TekumallaM97 fatcat:hftetvmbdfhbdhpmupk72hxmde

My-box representation for faulty CMOS circuits

J.-E. Chen, C.L. Lee, W.-Z. Shen
1990 IEE Proceedings G Circuits Devices and Systems  
A fault collapsing procedure is also derived to determine the representative set of prime faults (RSPF) for the transformed gate-level circuit.  ...  By applying this procedure to ten benchmark circuits, the number of faults can be reduced to approximately 15% of the original total faults, if the ten benchmark circuits are implemented in the fully CMOS  ...  Acknowledgment The authors would like to express their appreciation to the Centre for Gallium Arsenide VLSI Technology for creating an enthusiastic environment for GaAs research work in the area of the  ... 
doi:10.1049/ip-g-2.1990.0034 fatcat:5zymcfgktfe2vppxi4lcko4g5u

Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs [chapter]

Raimund Ubar, Lembit Jürimägi, Elmet Orasson, Jaan Raik
2016 IFIP Advances in Information and Communication Technology  
The paper presents a new method and an algorithm for structural fault collapsing to reduce the search space for test generation, to speed up fault simulation and to make the fault diagnosis easier in digital  ...  We introduce higher and lower bounds for fault collapsing and provide statistics of distribution of fault collapsing results over a broad set of benchmark circuits.  ...  Superposition of two SSBDDs Theorem 1 . 1 Let G(C) be the SSBDD model generated for the combinational circuit C by Procedure 1.  ... 
doi:10.1007/978-3-319-46097-0_2 fatcat:s55bdw6dkjaplh4i5v3wyv3q2u

Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits

Vamsi Boppana, W. Kent Fuchs
1998 Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design - ICCAD '98  
In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DATPG).  ...  Fault collapsing permits the organization of faults into disjoint partitions based on the indistinguishability relation.  ...  We first note the dynamic fault collapsing result for combinational circuits. Let us consider two faults /1 and / 2 .  ... 
doi:10.1145/288548.288593 dblp:conf/iccad/BoppanaF98 fatcat:ukcmua6etzhyhj2xjcpiutajxa

On the size and generation of minimal N-detection tests

K.R. Kantipudi, V.D. Agrawal
2006 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)  
We give an integer linear programming (ILP) algorithm for optimally minimizing a given test set for any given N ; in general, the value of N can be separately specified for each fault.  ...  The main result of this paper, proved as a theorem, is that a lower bound on the number of test vectors that detect each fault at least N times is N times the minimal test set size for N = 1.  ...  This circuit has a collapsed set of 237 detectable faults and 10 vectors were generated for each fault. Diagnostic simulation of these 2,370 vectors by Hope required 2.3 s.  ... 
doi:10.1109/vlsid.2006.125 dblp:conf/vlsid/Kantipudi06 fatcat:zojt5kneofc75bfxfpcvibouzy

Study on Test Compaction in High-Level Automatic Test Pattern Generation (ATPG) Platform

Ayub Chin Abdullah, Chia Yee Ooi
2013 Circuits and Systems  
This is because most of the high-level faults correlate with the gate-level collapsed faults especially at input/output of the modules in a circuit.  ...  In this research, we employ Chen's high-level fault model in the high-level ATPG.  ...  Checkpoint Theorem: A test set which detects all single stuck-at faults of the checkpoints of a combinational circuit detects all single stuck-at faults in that circuit.  ... 
doi:10.4236/cs.2013.44046 fatcat:poysiacqyjgzhlisdknlreuhhy

Bilateral Testing of Nano-scale Fault-Tolerant Circuits

Lei Fang, Michael S. Hsiao
2008 Journal of electronic testing  
In this paper, a new bilateral testing framework for nano circuits is proposed, where multiple stuck-at faults across different modules in a triple module redundancy (TMR) architecture are considered.  ...  In addition, a new test generator is presented for the bilateral testing that takes into account the enormous number of bilateral stuck-at faults possible with new types of guidance in the search, and  ...  For each TMR built from the circuit listed in Column 1, the number of uncollapsed stuck-at faults is first reported, followed by the collapsed stuck-at faults.  ... 
doi:10.1007/s10836-007-5041-3 fatcat:dajq4fxi2naidft2gujinw6f5m

Noise Threshold of Quantum Supremacy [article]

Keisuke Fujii
2016 arXiv   pre-print
Here we develop a threshold theorem for quantum supremacy with noisy quantum circuits in the pre-threshold region, where quantum error correction does not work directly.  ...  fault-tolerant quantum computation with the same circuit-level noise model.  ...  In the following, we apply the above theorem for two prototypical cases: concatenated fault-tolerant quantum computation [5] [6] [7] [8] and topological fault-tolerant quantum computation with the surface  ... 
arXiv:1610.03632v1 fatcat:hfhatfdxsvcyxa4vhtsgefub2i

Bilateral Testing of Nano-scale Fault-tolerant Circuits

Lei Fang, Michael Hsiao
2006 Proceedings (IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems)  
In this paper, a new bilateral testing framework for nano circuits is proposed, where multiple stuck-at faults across different modules in a triple module redundancy (TMR) architecture are considered.  ...  In addition, a new test generator is presented for the bilateral testing that takes into account the enormous number of bilateral stuck-at faults possible with new types of guidance in the search, and  ...  For each TMR built from the circuit listed in Column 1, the number of uncollapsed stuck-at faults is first reported, followed by the collapsed stuck-at faults.  ... 
doi:10.1109/dft.2006.17 dblp:conf/dft/FangH06 fatcat:s4dpelng4fbnfcjc6jdn5w2z24

Longest-path selection for delay test under process variation

Xiang Lu, Zhuo Li, Wangqi Qiu, D.M.H. Walker, Weiping Shi
2005 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
There are often multiple longest paths for each fault site in the circuit, due to different process conditions.  ...  Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay among all paths through  ...  fault sites in each circuit, column "# of paths for test" is the number of longest paths after collapsing.  ... 
doi:10.1109/tcad.2005.852674 fatcat:uhk5peeupja6zfcah7omcfmsry

Design for Testability of Sleep Convention Logic

Farhad A. Parsan, Scott C. Smith, Waleed K. Al-Assadi
2016 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In contrast to the NCL, there are currently no design for testability methodologies existing for the SCL.  ...  Testability is a major concern in industry for today's complex system-on-chip design.  ...  . 4) Faults in Register: According to Theorem 2, the traditional ATPG tools can be used to generate test patterns for detecting stuck-at faults in the SCL combinational blocks.  ... 
doi:10.1109/tvlsi.2015.2419816 fatcat:6x4q7ys4vnegxenrm6uv7ntwue

Test Generation for Combinational Quantum Cellular Automata (QCA) Circuits

P. Gupta, N.K. Jha, L. Lingappan
2006 Proceedings of the Design Automation & Test in Europe Conference  
In this paper, we present a test generation framework for testing of quantum cellular automata (QCA) circuits.  ...  This work is motivated by the fact that the stuck-at fault test set of a circuit is not guaranteed to detect all defects that can occur in its QCA implementation.  ...  CONCLUSIONS In this paper, we presented the first comprehensive testing methodology for combinational QCA circuits. First, we developed some fault collapsing theorems for majority circuits.  ... 
doi:10.1109/date.2006.244175 dblp:conf/date/GuptaJL06 fatcat:hzzxxocyljdvvpcfh7bql6datq

Use of fault dropping for multiple fault analysis

Y. Karkouri, E.M. Aboulhamid, E. Cerny, A. Verreault
1994 IEEE transactions on computers  
First, a fault collapsing phase is applied to the network, so that equivalent faults are eliminated.  ...  It is shown that the set of frontier faults is equivalent to the set of multiple faults. Given an input vector, we evaluate the fault free circuit and then propagate fault effects.  ...  Example: For the circuit in Fig. 1 , the number of frontier faults is only 16 compared to 80 multiple faults after collapsing.  ... 
doi:10.1109/12.250613 fatcat:3jgxjgdoyjc25p7d2423zps5mu

Quantum advantage of unitary Clifford circuits with magic state inputs

Mithuna Yoganathan, Richard Jozsa, Sergii Strelchuk
2019 Proceedings of the Royal Society A  
Along the way, we give an extension of the Gottesman-Knill theorem that applies to universal computation, showing that for Clifford circuits with joint stabilizer and non-stabilizer inputs, the stabilizer  ...  part can be eliminated in favour of classical simulation, leaving a Clifford circuit on only the non-stabilizer part.  ...  Montanaro for helpful discussions and clarifications. We thank Ryuhei Mori and an anonymous referee for pointing out approach (b) in theorem 5.1 to us.  ... 
doi:10.1098/rspa.2018.0427 pmid:31236039 pmcid:PMC6545052 fatcat:3yehig77e5g7pb2vahesxssc54
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