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Revizor: Testing Black-box CPUs against Speculation Contracts [article]

Oleksii Oleksenko, Christof Fetzer, Boris Köpf, Mark Silberstein
2022 arXiv   pre-print
We propose a Model-based Relational Testing (MRT) technique to empirically assess the CPU compliance with these specifications.  ...  Such vulnerabilities often stay undetected for a long time as we lack the tools for systematic testing of CPUs to find them.  ...  Using many hardware registers and larger sandbox results in low input effectiveness (CH2), as it increases the likelihood of unique contract traces that cannot be used for relational testing.  ... 
arXiv:2105.06872v3 fatcat:jjm3hvrm5jezpnpjra7yu7rune

Improved device driver reliability through hardware verification reuse

Leonid Ryzhyk, John Keys, Balachandra Mirla, Arun Raghunath, Mona Vij, Gernot Heiser
2011 Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems - ASPLOS '11  
We apply this workflow to develop and test drivers for four different I/O devices and demonstrate that it improves the driver test coverage and allows detecting driver defects that are extremely hard to  ...  find using conventional testing techniques.  ...  NICTA is funded by the Australian Government's Department of Communications, Information Technology, and the Arts and the Australian Research Council through Backing Australia's Ability and the ICT Research  ... 
doi:10.1145/1950365.1950383 dblp:conf/asplos/RyzhykKMRVH11 fatcat:v62xuybdibcl5b7e25llnella4

Improved device driver reliability through hardware verification reuse

Leonid Ryzhyk, John Keys, Balachandra Mirla, Arun Raghunath, Mona Vij, Gernot Heiser
2012 SIGPLAN notices  
We apply this workflow to develop and test drivers for four different I/O devices and demonstrate that it improves the driver test coverage and allows detecting driver defects that are extremely hard to  ...  find using conventional testing techniques.  ...  NICTA is funded by the Australian Government's Department of Communications, Information Technology, and the Arts and the Australian Research Council through Backing Australia's Ability and the ICT Research  ... 
doi:10.1145/2248487.1950383 fatcat:dyb2nb2275dudkifp5tsuzfpva

Improved device driver reliability through hardware verification reuse

Leonid Ryzhyk, John Keys, Balachandra Mirla, Arun Raghunath, Mona Vij, Gernot Heiser
2011 SIGARCH Computer Architecture News  
We apply this workflow to develop and test drivers for four different I/O devices and demonstrate that it improves the driver test coverage and allows detecting driver defects that are extremely hard to  ...  find using conventional testing techniques.  ...  NICTA is funded by the Australian Government's Department of Communications, Information Technology, and the Arts and the Australian Research Council through Backing Australia's Ability and the ICT Research  ... 
doi:10.1145/1961295.1950383 fatcat:izxco5xrevelxehk4d7jtdtdfu

Improved device driver reliability through hardware verification reuse

Leonid Ryzhyk, John Keys, Balachandra Mirla, Arun Raghunath, Mona Vij, Gernot Heiser
2011 SIGPLAN notices  
We apply this workflow to develop and test drivers for four different I/O devices and demonstrate that it improves the driver test coverage and allows detecting driver defects that are extremely hard to  ...  find using conventional testing techniques.  ...  NICTA is funded by the Australian Government's Department of Communications, Information Technology, and the Arts and the Australian Research Council through Backing Australia's Ability and the ICT Research  ... 
doi:10.1145/1961296.1950383 fatcat:chxoqus34ja33kwlqdgkv72lju

The challenge of interoperability

Huafeng Yu, Prachi Joshi, Jean-Pierre Talpin, Sandeep Shukla, Shinichi Shiraishi
2015 Proceedings of the 52nd Annual Design Automation Conference on - DAC '15  
The main advantages of the proposed approach include its pervasive use of formal methods, architecture analysis and design language (AADL) and associated tools, a novel timing annex for AADL with an expressive  ...  A novel model-based formal integration framework is being developed to enable architecture modeling, timing specification, formal semantics, design by contract and optimization in the system-level design  ...  The formal contracts, used for describing the functional and non-functional specifications of the components, consider the archi-tecture and platform models as well as their associated properties.  ... 
doi:10.1145/2744769.2747945 dblp:conf/dac/YuJTSS15 fatcat:dlsu7o7t4bgebgx7bv4wrlk7z4

VERIFICATION OF OPERATING SYSTEM COMPONENTS

Victor Kuliamin, Alexander Petrenko, Alexey Khoroshilov
2017 System Informatics  
By industrial OS we mean a system actively used in some industrial domain, elaborated and maintained for a significant time, not a proof-of-concept OS developed with mostly research intentions.  ...  We consider decomposition of this goal into tasks related with various functional components of OS and various properties under verification, and application of different verification methods to those  ...  The first such results are related with KVEST [7] , a method for test generation based on formal specifications of functional behavior in form of software contracts, used to construct several test suites  ... 
doi:10.31144/si.2307-6410.2017.n10.p11-22 fatcat:o7wstrujt5b67lkwodyzequmha

A Model–Based Design Methodology with Contracts to Enhance the Development Process of Safety–Critical Systems [chapter]

Andreas Baumgart, Philipp Reinkemeier, Achim Rettberg, Ingo Stierand, Eike Thaden, Raphael Weber
2010 Lecture Notes in Computer Science  
The meta-model of Heterogeneous Rich Component (HRC) is extended to a Common System Meta-Model (CSM) that benefits from the semantic foundation of HRC and provides analysis techniques such as compatibility  ...  In this paper a new methodology to support the development process of safety-critical systems with contracts is described.  ...  However, modeling concepts for behavioral specification of functions are not part of EAST-ADL.  ... 
doi:10.1007/978-3-642-16256-5_8 fatcat:7jk7vzsxkzeflciu4uol3wbybe

From Design Contracts to Component Requirements Verification [article]

Jing Liu and John D. Backes and Darren Cofer and Andrew Gacek
2016 arXiv   pre-print
During the development and verification of complex airborne systems, a variety of languages and development environments are used for different levels of the system hierarchy.  ...  This paper presents a tool-supported export technique that translates high-level requirements from the software architecture modeling environment into observers of requirements that can be used for verification  ...  This work was funded by NASA under contract NNA13AA21C (Compositional Verification of Flight Critical Systems).  ... 
arXiv:1603.02130v2 fatcat:yqkz5g7avbhujfcekz5f2cwy5u

Design and Testing Ways for Mechatronic Systems

Liviu Mihai Sima
2022 International Journal on Cybernetics & Informatics  
Interfaces, which are hardware and software, define the functionality of the system by inserting functions from one component to another.  ...  The article describes the method of selecting the components and the way of testing the system during production. Finally, the system must meet the requirements of the customer.  ...  They must meet the specifications and requirements so that they provide us with the basis for functional structural derivation. The hierarchical structure used for functional modeling.  ... 
doi:10.5121/ijci.2022.110206 fatcat:c74i55fgizd6rkxtplhhjnn6me

AN ARCHITECTURE DESCRIPTION LANGUAGE FOR IN-VEHICLE EMBEDDED SYSTEM DEVELOPMENT

Jean-Pierre Elloy, Françoise Simonot-Lion
2002 IFAC Proceedings Volumes  
This language supports the AEE design process, and is used by all designers as the backbone of the architecture development. Finally it is used to define reusable architecture objects.  ...  This paper presents the AEE project (Embedded Electronic Architecture), a French cooperative research and development program whose purpose is to specify new solutions for in-vehicle embedded system development  ...  for their essential contributions to the definition of the AIL language.  ... 
doi:10.3182/20020721-6-es-1901.00060 fatcat:4iypmsyg3jaile6uuaf5x5ybsq

Specification-driven testbench development for synchronous parallel-pipeline designs

Mikhail Chupilko, Alexander Kamkin
2009 2009 NORCHIP  
The important feature of the proposed method is that specifications are used to perform all tasks of functional testbenches: checking of design correctness, estimation of test completeness, and generation  ...  The approach was successfully used in several industrial projects on hardware verification.  ...  The distinction feature of the approach is that it does not require two different models for checking design correctness and for test sequence generation.  ... 
doi:10.1109/norchp.2009.5397808 fatcat:akx3mini3na2dgvegea6pfgsje

A Decision Support Tool for Optimising Support Site Configuration of Functional Products

Petter Kyösti, Sean Reed, Sven Sjödin
2014 Procedia CIRP  
This paper discusses a decision support tool designed for use by management and engineering personnel at Functional Product providers to analyse and optimize the performance of their support base configuration  ...  It features a graphical user interface for configuration customization, simulation modelling to predict performance and outputs a wide range of analytics that can be used to compare and optimize configurations  ...  Acknowledgement Petter Kyösti gratefully acknowledges the contribution from the Swedish Governmental Agency for Innovation Systems (VINNOVA) for funding The Faste Laboratory, Centre for Functional Product  ... 
doi:10.1016/j.procir.2014.06.155 fatcat:qxviwh46ajenhjp426ftxfzmka

Quantified economic and environmental values through Functional Productization - A simulation approach

Sean Reed, Magnus Karlberg, Petter Kyösti, Daria Sas
2018 Environmental impact assessment review  
whilst giving providers freedom to choose and retain ownership of the supplied hardware and services.  ...  Traditionally, industrial companies choose and purchase hardware and maintenance support to fulfil their functional requirements.  ...  H1 … H20 C1 … C20 S1 … S20 Figure 6 -Genome representing a solution to the customer functional requirements, where Hn is an integer representing the choice from the feasible set of hardware for functional  ... 
doi:10.1016/j.eiar.2018.03.006 fatcat:qozyunn2vvh3lf4rpgujc2y3cy

Using unified power format standard concepts for power-aware design and verification of systems-on-chip at transaction level

O. Mbarek, A. Pegatoquet, M. Auguin
2012 IET Circuits, Devices & Systems  
A generic framework that abstracts relevant concepts of the IEEE 1801 unified power format standard and implements assertion-based contracts is used throughout the methodology.  ...  Transaction level modelling allows a rapid exploration, verification and evaluation of alternative power-management architectures and strategies.  ...  TL-design. † Functional components: represent IPs of the considered TL-model. † Mixed components: represent PMU modules and their sub-modules (i.e.  ... 
doi:10.1049/iet-cds.2011.0352 fatcat:jszag4rq4zfcjgswfbd3dvbrwm
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