A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is `application/pdf`

.

## Filters

##
###
The synthesis of combinational logic to generate probabilities

2009
*
Proceedings of the 2009 International Conference on Computer-Aided Design - ICCAD '09
*

-through

doi:10.1145/1687399.1687470
dblp:conf/iccad/QianRBL09
fatcat:c32iduunibenvnq5oe6j6cx5z4
*combinational**logic*. ... In this work, we demonstrate a novel technique for synthesizing*logic*that*generates*new*probabilities*from a given set*of**probabilities*. ... He focused on synthesizing a sequential state machine*to**generate**the*required*probabilities*. • In recent work,*the*proponents*of*PCMOS discussed*the*problem*of*synthesizing*combinational**logic**to**generate*...##
###
Automated Evolutionary Design of Fault-Tolerant Logic Circuits

2019
*
Problems of advanced micro- and nanoelectronic systems development
*

This paper presents a method for

doi:10.31114/2078-7707-2019-1-2-6
fatcat:tda2qnjyarbcdaqcfllymg5i44
*combinational*circuits*synthesis*based on*general*principles*of*evolutionary algorithms. ... This method allows synthesizing comparatively small*logic*circuits that are resistant*to*random failures induced by hits*of*heavy charged particles. ... Within*the*proposed approach, we suggest*to**generalize**the*problem*of*improving fault tolerance*of*a given*logic*circuit*to**the*problem*of*fault-tolerant*combinational*circuit*synthesis*. ...##
###
Synthesizing Combinational Logic to Generate Probabilities: Theories and Algorithms
[chapter]

2010
*
Advanced Techniques in Logic Synthesis, Optimizations and Applications
*

Synthesizing

doi:10.1007/978-1-4419-7518-8_18
fatcat:5yxyqvplgbfifpvdaq5gvbjpei
*Combinational**Logic**to**Generate**Probabilities*: Theories and Algorithms We find that*the*other*combinational**synthesis*commands*of*ABC such as "rewrite" do not affect*the*depth or ... Elements that Can*Generate*Arbitrary Decimal*Probabilities*Synthesizing*Combinational**Logic**to**Generate**Probabilities*: Theories and Algorithms Synthesizing*Combinational**Logic**to**Generate**Probabilities*... w.r.t.*the*first pair has more ANDs} 14: return -1; 15: else 16: return 0; ...##
###
Automated phase assignment for the synthesis of low power domino circuits

1999
*
Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99
*

Hence, we study

doi:10.1145/309847.309964
dblp:conf/dac/PatraN99
fatcat:75livrbjuzdg3jmyoak5r2qgmi
*synthesis*techniques that allow designers*to*take advantage*of**the*speed*of*domino circuits while at*the*same time*to*minimize total power consumption. ... Specifically, in this paper we present three results related*to*automated phase assignment for*the**synthesis**of*low power domino circuits: (1) We demonstrate that*the*choice*of*phase assignment at*the*... , and*the*team for their valuable feedback about this research. ...##
###
Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches

2016
*
IEEE Transactions on Reliability
*

However,

doi:10.1109/tr.2016.2604918
fatcat:wg3skzzk4vfpdoslr7hqucvb6i
*generating*an optimal redundant*logic*circuit that is able*to*mask*the*faults with*the*highest*probability*while minimizing*the*area overheads is a challenging problem. ... In this work we propose and compare two new approaches*to**generate*approximate*logic*circuits*to*be used in a TMR schema. ... Without loss*of**generality*, we will focus on*combinational*circuits.*The*extension*to*sequential circuits is trivial by applying TMR*to**the*sequential elements along with*the**combinational*elements. ...##
###
Impact of Logic Synthesis on Soft Error Rate of Digital Integrated Circuits

2012
*
2012 IEEE Computer Society Annual Symposium on VLSI
*

*Logic*

*synthesis*tools use a

*combination*

*of*both heuristic and rule-based algorithms

*to*map a Boolean network

*to*a physical implementation. ...

*The*

*probability*

*of*

*generation*is described as

*the*ratio

*of*

*the*critical area

*of*node

*to*

*the*total circuit area. ...

##
###
DeepSAT: An EDA-Driven Learning Framework for SAT
[article]

2022
*
arXiv
*
pre-print

*To*effectively train

*the*

*generative*model, with

*the*help

*of*

*logic*simulation tools, we obtain

*the*

*probabilities*

*of*nodes in

*the*AIG being

*logic*'1' as rich supervision. ... Specifically, we first resort

*to*advanced

*logic*

*synthesis*algorithms

*to*pre-process SAT instances into optimized and-inverter graphs (AIGs). ... Effectiveness

*of*

*Logic*

*Synthesis*

*To*validate

*the*effectiveness

*of*our proposed data transformation based on

*the*

*logic*

*synthesis*, we construct two datasets: one is

*the*original dataset with

*logic*

*synthesis*...

##
###
Sequential logic optimization for low power using input-disabling precomputation architectures

1998
*
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
*

*The*very power

*of*this architecture makes

*the*

*synthesis*

*of*precomputation

*logic*a challenging problem. We present a method

*to*automatically synthesize precomputation

*logic*for this architecture. ... We target a

*general*precomputation architecture for sequential

*logic*circuits, and show that it is significantly more powerful than

*the*architecture previously treated in

*the*literature. ... We used a

*general*delay model where

*the*gate delays were obtained from

*the*MSU

*generic*library.

*The*rugged script

*of*SIS was used

*to*optimize

*the*precompute

*logic*. ...

##
###
Page 3386 of Mathematical Reviews Vol. , Issue 81H
[page]

1981
*
Mathematical Reviews
*

“In this paper,

*the*concept*of**the*inversion*of**the**logic*function, used so effectively in*the**synthesis**of*single-output negative-gate networks, is extended*to*a*combinational**logic*function, and*the*... This note refers*to**the*problem*of**the**synthesis**of*a*logical*scheme for a probabilistic converter which realizes*the*discrete*probability*distribution p,,---,p,, p;)>0, 27%.,p,=1. ...##
###
Noise Tolerant Stochastic Logic Gate Circuits Synthesis using Genetic Algorithms

2015
*
International Journal of Computer Applications
*

In this paper we propose a method for

doi:10.5120/ijca2015905651
fatcat:jb4esvhdtbcu7a7kix3npgjmv4
*synthesis**of**combinational*networks using non conventional*logic*gates. ... We propose a solution for*the**synthesis**of*SLGs*combinational*networks able*to*produce a network operating fault tolerant in different environmental conditions, i.e. different levels*of*noise. ...*The*ability*of*a*combinational*circuit*to*be more robust*to**the*noise takes its toll, usually in complexity or number*of**logic*gate used. ...##
###
Parsimonious Circuits for Error-Tolerant Applications through Probabilistic Logic Minimization
[chapter]

2011
*
Lecture Notes in Computer Science
*

Contrary

doi:10.1007/978-3-642-24154-3_21
fatcat:swzrk2burrfpjglha5rzvgf4tu
*to**the*existing techniques*to*realize inexact circuits that relied mostly on scaling*of*supply voltage or pruning*of*"leastsignificant" components in conventional correct circuits*to*achieve cost ... Extensive simulations*of**the*datapath elements designed using*the*proposed technique demonstrate that normalized gains as high as 2X-9.5X in*the*Energy-Delay-Area product can be obtained when compared ... Hence,*the**probability**of*an input*combination*occurring at a node is*generally*either (a) only dependent on*the*input test vectors (such as full adders in ripple carry adder (RCA) and external full adder ...##
###
RP-SYN: synthesis of random pattern testable circuits with test point insertion

1999
*
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
*

RP-SYN takes as an input a two-level description

doi:10.1109/43.775638
fatcat:svkhd3wlt5hktbp46ujlawancu
*of*a circuit and a constraint on*the*minimum fault detection*probability*(threshold below which faults are considered randompattern-resistant), and*generates*... By moving*the*task*of*test point insertion from*the*back-end into*the**synthesis*process, RP-SYN reduces design time and enables better optimization*of**the*resulting implementation. ...*The*number*of*input*combinations*that detect*the*fault is then divided by*the*total number*of*input*combinations*, , where is*the*number*of*primary inputs,*to*give*the*fault detection*probability*. ...##
###
BIST for systems-on-a-chip

1998
*
Integration
*

Special emphasis is put on deterministic BIST methods as they do not require any modifications

doi:10.1016/s0167-9260(98)00021-2
fatcat:qenkm6odojampcjqguhbco6l6m
*of**the*core under test and help*to*protect intellectual property (IP). ... An increasing part*of*microelectronic systems is implemented on*the*basis*of*predesigned and preverified modules, so-called cores, which are reused in many instances. ... Figure 14 shows*the*structure*of*a synchronous control unit with*the*binary input variables x x m 3)*Logic**synthesis*:*The*uniquely defined Boolean functions ¢ l and ¢ d have*to*be implemented by*combinational*...##
###
Signature-Based SER Analysis and Design of Logic Circuits

2009
*
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
*

We explore

doi:10.1109/tcad.2008.2009139
fatcat:a6g4gyx6drdwheewfp2tjac7zq
*the*use*of*signatures, i.e., partial truth tables*generated*via bit-parallel functional simulation, during soft error analysis and*logic**synthesis*. ... We observe that*the*SER*of*a*logic*circuit is closely related*to*various testability parameters, such as signal observability and*probability*. ... This use*of*ADDs in SER analysis is different from*the*use*of*BDDs in*logic**synthesis**to*represent Boolean functions.*The*latter is*generally*much more efficient. ...##
###
Protecting Combinational Logic Synthesis Solutions

2006
*
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
*

In order

doi:10.1109/tcad.2006.882490
fatcat:jlml3e7czzgatfdnwh6qfnkcxa
*to*evaluate*the*developedwatermarking method,*the*authors applied it*to*a standard set*of*real-life benchmarks, where high*probability**of*authorship was achieved with negligible overhead on solution ...*The*authors propose a new method for intellectual-property protection that relies upon design watermarking at*the**combinational*-*logic*-*synthesis*level. ...*Combinational**Synthesis**Combinational*-*logic**synthesis*has been thoroughly studied. ...
« Previous

*Showing results 1 — 15 out of 134,444 results*