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The structure of chips and links comprising the IBM eServer z990 I/O subsystem

E. W. Chencinski, M. J. Becht, T. E. Bubb, C. G. Burwick, J. Haess, M. M. Helms, J. M. Hoke, T. Schlipf, J. M. Turner, H. Ulland, M. H. Walz, C. H. Whitehead (+1 others)
2004 IBM Journal of Research and Development  
I/O topology Figure 1 shows the structure of the z990 central electronic complex (CEC) and its interconnection to external nets  ...  The performance of large servers is to a high degree determined by their I/O subsystems.  ...  Helms IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schoenaicherstrasse 220, 71032 Boeblingen, Germany (helms@de.ibm.com). Mr  ... 
doi:10.1147/rd.483.0449 fatcat:syzxyvcop5fphkk6zf23lf5yke

Reliability, availability, and serviceability (RAS) of the IBM eServer z990

M. L. Fair, C. R. Conklin, S. B. Swaney, P. J. Meaney, W. J. Clarke, L. C. Alves, I. N. Modi, F. Freier, W. Fischer, N. E. Weber
2004 IBM Journal of Research and Development  
The IBM eServer zSeries Model z990 offers customers significant new opportunity for server growth while preserving and enhancing server availability.  ...  Processor subsystem Concurrent book add The z990 provides the capability of concurrently upgrading the server model by adding the second, third, or fourth processor book, which increases physical processors  ...  Hardware view The channel subsystem structure comprises CPs, SAPs, MBAs, enhanced self-timed interface (eSTI) ports, and the high-density I/O cage.  ... 
doi:10.1147/rd.483.0519 fatcat:lcubvnb5zzd6nlxpjdfgklrrbq

Accelerating system integration by enhancing hardware, firmware, and co-simulation

K.-D. Schubert, E. C. McCain, H. Pape, K. Rebmann, P. M. West, R. Winkelmann
2004 IBM Journal of Research and Development  
System integration of an IBM eServer z990 begins when a z990 book, which houses the main processors, memory, and I/O adapters, is installed in a z990 frame, Licensed Internal Code is "booted" in the service  ...  This paper focuses primarily on the hardware subsystem verification of the CLK chip [which is the interface between the central electronic complex (CEC) and the service element (SE)] and on enhanced co-simulation  ...  It is critical to have I/O chips in the model in IML step 5, where the I/O hardware reset is executed and the STI links are initialized.  ... 
doi:10.1147/rd.483.0569 fatcat:6hlhb4x37vc3pjfmbzkkpfastm

IBM eServer z990 improvements in firmware simulation

M. Stetter, J. von Buttlar, P. T. Chan, D. Decker, H. Elfering, P. M. Gioquindo, T. Hess, S. Koerner, A. Kohler, H. Lindner, K. Petri, M. Zee
2004 IBM Journal of Research and Development  
path of firmware interaction between the CEC and the I/O channels.  ...  With the IBM eServer z900, simulation methods and tools for verification of code that is to be embedded in the memory of the system (firmware) were introduced.  ...  CECSIM enhancements for the z990 The use of the firmware simulator CECSIM during the development of the IBM eServer* z900 was very successful [3] .  ... 
doi:10.1147/rd.483.0583 fatcat:l6dxqdpek5htpa5pjzlx2yadke

First- and second-level packaging of the z990 processor cage

T.-M. Winkel, W. D. Becker, H. Harrer, H. Pross, D. Kaller, B. Garben, B. J. Chamberlin, S. A. Kuppinger
2004 IBM Journal of Research and Development  
In this paper, we describe the challenging first-and secondlevel packaging technology of a new system packaging architecture for the IBM eServer z990.  ...  The z990 dramatically increases the volumetric processor density over that of the predecessor z900 by implementing a super-blade design comprising four node cards.  ...  Acknowledgment The authors would like to thank Roland Frech for performing the VHDM connector measurements and for providing the coupling data in Table 4 .  ... 
doi:10.1147/rd.483.0379 fatcat:hr27o73sjjas7ii7km6q3suk7m

The z990 first error data capture concept

S. Koerner, R. Bawidamann, W. Fischer, U. Helmich, D. Klodt, B. K. Tolan, P. Wojciak
2004 IBM Journal of Research and Development  
z990 system components relevant to FEDC The z990 system structure supported by the FEDC concept comprises the host firmware-I/O subsystem (IOSS), processing unit subsystem (PSS), and logical partitioning  ...  of an I/O card or the CEC.  ...  Wojciak, as a Senior Engineer, continues to enjoy devising new and creative ways of making the zSeries systems fail, all in the name of fault-tolerant computing.  ... 
doi:10.1147/rd.483.0557 fatcat:vusiun3cmzag5hvjk3oyzzbmde

Functional verification of a frequency-programmable switch chip with asynchronous clock sections

B. Hoppe, B. Arthur-Mensah, E. W. Chencinski, S. Joseph, H. Kumar, J. F. Silverio
2004 IBM Journal of Research and Development  
An integral part of the IBM eServer z990 I/O subsystem is the self-timed interface (STI) switch chip.  ...  The STI switch is an application-specific integrated circuit (ASIC) designed to provide high I/O connectivity and high bandwidth within the system.  ...  Introduction The z990 eServer* I/O subsystem comprises an architecture providing I/O connectivity, networking connectivity, and intersystems connectivity.  ... 
doi:10.1147/rd.483.0461 fatcat:zt27n46l5baddl7lpkbefj7v4e